Miller plateau in Buck Converter Synchronous

[Occio]

Hi, I can't understand why in hard switching there is Miller plateau but no presence of it in soft switching. I don't know if I'm thinking well considering Miller plateau effect: when, for example in the high-side FET turn-on with high load, when ids = iL, vgs = Vth + iL/gm and so it remains constant during vds reaches zero. But why in soft switching it doesn't happen? I read that I have to consider the polarity of Cgd: in hard switching vgd goes from negative to positive values while in soft switching it remains always positive. How can I connect the two things?
Thanks!

 

[unclejed613]

https://www.vishay.com/docs/73217/an608a.pdf

because you have two capacitances at work, Cgd and Cgs.

from page 3

The slope of the Miller Plateau is generally shown to have a zero, or a near-zero slope, but this gradient depends on the division of drive current between Cgd and Cgs. If the slope is non-zero then some of the drive current is flowing into Cgs. If the slope is zero then all the drive current is flowing into Cgd. This happens if the Cgd x Vgd product increases very quickly and all the drive current is being used to accommodate the change in voltage across Cgd. As such, QGD is the charge injected into the gate during the time the device is in the Miller Plateau. It should be noted that once the plateau is finished (when Vds reaches its on-state value), Cgd becomes constant again and the bulk of the current flows into Cgs. The gradient is not as steep as it was in the first period t2, because Cgd is much larger and closer in magnitude to that of Cgs.

 

[Occio]

https://www.vishay.com/docs/73217/an608a.pdf

because you have two capacitances at work, Cgd and Cgs.

from page 3

Thank you, it was what I was looking for. I read some time ago this paper from Vishay, but I didn't remember it anymore. Thanks again!