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migrating asm code 16C84 to 16C710

Discussion in 'Microcontrollers' started by Brute, Oct 31, 2012.

  1. Brute

    Brute New Member

    Joined:
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    Sorry send you the wrong code, this is what I had note that ADCON1 EQU 88H, isn't that the same?

    TITLE "CTCSS Encoder v1.4 for 16C710"
    ; 14-4-99
    ; Assemble with MPASM
    ; See below for wiring details
    ;
    LIST P=16C710
    __CONFIG 3FF9H ;XTAL OSC @4Mhz,NO WATCHDOG,PWRRST,NO CP.
    __IDLOCS 1234
    ERRORLEVEL -302
    ;
    CNT1 EQU 0CH ;PRESCALLER COUNTER REG 1
    CNT2 EQU 0DH ;PRESCALLER COUNTER REG 2
    CNT3 EQU 0EH ;PRESCALLER COUNTER REG 3
    TONREG EQU 0FH ;REGISTER FOR TONE NUMBER
    PRES1 EQU 10H ;PRESCALLER STORE 1
    PRES2 EQU 11H ;PRESCALLER STORE 2
    PRES3 EQU 12H ;PRESCALLER STORE 3
    PORTA EQU 5
    PORTB EQU 6
    TRISA EQU 85H
    TRISB EQU 86H
    ADCON1 EQU 88H
    OPTREG EQU 81H
    PC EQU 2
    PULLUP EQU 7
    STATUS EQU 3
    INTCON EQU 0BH
    GIE EQU 7
    RBIE EQU 3
    RBIF EQU 0
    RP0 EQU 5
    OUT EQU 2
    PTT EQU 7
    ;
    GOTO START
    ORG 00C8
    START BSF STATUS,RP0 ;SELECT REG BANK 1
    BSF TRISB,PTT ;SETUP RB7 AS INPUT FOR PTT
    BCF TRISA,OUT ;SETUP RA2 AS OUTPUT FOR TONE
    BCF OPTREG,PULLUP ;SET PULLUP RESISTORS ON PORTB
    MOVLW 0xFF ; SET PORTB AS I/Ps
    MOVWF TRISB ; RB0-RB5 FOR SWITCH INPUTS
    CLRF ADCON1
    ;

    BCF STATUS,RP0 ;SELECT REG BANK 0
    BCF INTCON,GIE ;DISABLE GIE INTERUPTS
    BSF INTCON,RBIE ;ENABLE PORT B CHANGE INTERUPT
    MOVF TRISB,W ;READ DIP SWITCHES INTO W
    MOVWF TONREG ;STORE IN 0F REG
    BCF TONREG,6 ; CLEAR BITS 6&7 AS
    BCF TONREG,7 ; THEY ARE IRRELAVANTS
    MOVF TONREG,W ;RE-STORE INTO W
    ADDWF TONREG,F ; MULTIPLY BY 3
    ADDWF TONREG,F ; FOR TONE TABLE OFFSET
    ;
    MOVF TONREG,W ;RELOAD TO W FOR OFFSET
    CALL TONTBL ;GOTO TONE LOOKUP TABLE
    MOVWF PRES1 ;STORE FIRST VALUE FROM TABLE
    ;
    INCF TONREG,F ;INCREMENT FOR NEXT TABLE VALUE
    MOVF TONREG,W ;RELOAD W FOR OFFSET
    CALL TONTBL ;GOTO TONE LOOKUP TABLE
    MOVWF PRES2 ;STORE SECOND VALUE FROM TABLE
    ;
    INCF TONREG,F ;INCREMENT FOR NEXT TABLE VALUE
    MOVF TONREG,W ;RELOAD W FOR OFFSET
    CALL TONTBL ;GOTO TONE LOOKUP TABLE
    MOVWF PRES3 ;STORE THIRD VALUE FROM TABLE
    ;
    ;
    RELOAD
    MOVF PRES1,W ;LOAD W WITH PRESET FOR 1
    MOVWF CNT1 ;PRELOAD PRESCALLER 1
    MOVF PRES2,W ;LOAD W WITH PRESET FOR 3
    MOVWF CNT3 ;PRELOAD PRESCALLER 3
    MOVF PRES3,W ;LOAD W WITH PRESET FOR 2 READY
    PTTCHK
    BTFSC PORTB,PTT ;TEST PTT LINE
    GOTO WAIT ;SLEEP TILL LOW
    CALL CHORUS ;DO DIVIDER/PRESCALLER ROUTINE
    ;
    OUTPUT
    BTFSS PORTA,OUT ;TEST O/P HI OR LO AT PRESENT
    GOTO HI ;IF LO GO SET HI
    GOTO LO ;IF HI GO SET LO
    ;
    HI
    NOP ;BALANCE OUT CYCLE TIME MARK&SPACE
    BSF PORTA,OUT ;MAKE O/P HI
    GOTO RELOAD ;RETURN TO START OF CYCLE
    ;
    LO
    BCF PORTA,OUT ;MAKE O/P LO
    GOTO RELOAD ;RETURN TO START OF CYCLE
    ;
    CHORUS
    PRE1
    DECFSZ CNT1,F ;DECREMENT PRESCALLER 1
    GOTO PRE2
    GOTO FINE ;CALL FINE ADJUST SUBROUTINE
    PRE2 MOVWF CNT2 ;RELOAD PRESCALLER 2
    ;
    PREE DECFSZ CNT2,F ;DECREMENT PRESCALLER 2
    GOTO PREE ;GO BACK AND DECREMENT PRE2 TILL 00
    ;
    GOTO PRE1 ;GO BACK AND DECREMENT PRE1 TILL 00
    ;
    FINE DECFSZ CNT3,F ;DECREMENT PRESCALLER 3
    GOTO FINE ;GO BACK AND DECREMENT PRE3 TILL 00
    RETURN ;RETURN TO CHANGE O/P AND CHECK PTT ETC
    ;
    WAIT
    BCF INTCON,RBIF ;CLEAR PORT B CHANGE INT FLAG
    SLEEP ;SLEEP AND WAIT FOR PTT
    NOP
    BCF INTCON,GIE ;DISABLE GLOBAL INTERUPTS AGAIN
    GOTO PTTCHK ;CHECK IF PTT PASSES TEST
    ;
    ;
    ;
    ;TONES TABLE AT 0008H
    ORG 0007H
    TONTBL
    ADDWF PC,F ; W+PC ->PC, JUMP DOWN TABLE
    ;
    ;
    ; 16C710 PIN
    ; 11 10 9 8 7 6
    ; TONE FREQ RB5 RB4 RB3 RB2 RB1 RB0
    ;
    DT 02,01,0x9D ; 000 1Khz TEST 0 0 0 0 0 0
    DT 86,82,10 ; 001 67.0 0 0 0 0 0 1
    DT 81,85,10 ; 002 69.4 * 0 0 0 0 1 0
    DT 84,80,0x0F ; 003 71.9 0 0 0 0 1 1
    DT 7F,85,0x0F ; 004 74.4 0 0 0 1 0 0
    DT 7B,7C,0x0F ; 005 77.0 0 0 0 1 0 1
    DT 76,86,0x0F ; 006 79.7 0 0 0 1 1 0
    DT 72,82,0x0F ; 007 82.5 0 0 0 1 1 1
    DT 74,8F,0x0E ; 008 85.4 0 0 1 0 0 0
    DT 63,91,10 ; 009 88.5 0 0 1 0 0 1
    DT 5F,9A,10 ; 010 91.5 0 0 1 0 1 0
    DT 5B,47,11 ; 011 94.8 0 0 1 0 1 1
    DT 55,88,11 ; 012 97.4 0 0 1 1 0 0
    DT 56,49,11 ; 013 100.0 0 0 1 1 0 1
    DT 09,6E,0xB9 ; 014 103.5 0 0 1 1 1 0
    DT 08,81,0xC9 ; 015 107.2 0 0 1 1 1 1
    DT 0A,71,98 ; 016 110.9 0 1 0 0 0 0
    DT 0B,76,83 ; 017 114.8 0 1 0 0 0 1
    DT 0A,0xCA,83 ; 018 118.8 0 1 0 0 1 0
    DT 0A,9A,83 ; 019 123.0 0 1 0 0 1 1
    DT 09,0xF1,83 ; 020 127.3 0 1 0 1 0 0
    DT 08,93,9D ; 021 131.8 0 1 0 1 0 1
    DT 07,94,0xB0 ; 022 136.5 0 1 0 1 1 0
    DT 07,7C,0xAD ; 023 141.3 0 1 0 1 1 1
    DT 07,85,0xA5 ; 024 146.2 0 1 1 0 0 0
    DT 08,7B,89 ; 025 151.4 0 1 1 0 0 1
    DT 08,80,83 ; 026 156.7 0 1 1 0 1 0
    DT 07,0xA2,90 ; 027 159.8 * 0 1 1 0 1 1
    DT 08,47,86 ; 028 162.2 0 1 1 1 0 0
    DT 07,60,95 ; 029 165.5 * 0 1 1 1 0 1
    DT 08,86,78 ; 030 167.9 0 1 1 1 1 0
    DT 07,92,87 ; 031 171.3 * 0 1 1 1 1 1
    DT 07,90,85 ; 032 173.8 1 0 0 0 0 0
    DT 07,7D,85 ; 033 177.3 * 1 0 0 0 0 1
    DT 09,5A,66 ; 034 179.9 1 0 0 0 1 0
    DT 09,48,66 ; 035 183.5 * 1 0 0 0 1 1
    DT 07,9E,78 ; 036 186.2 1 0 0 1 0 0
    DT 08,0xBB,60 ; 037 189.9 * 1 0 0 1 0 1
    DT 09,4C,60 ; 038 192.8 1 0 0 1 1 0
    DT 08,9D,60 ; 039 196.6 * 1 0 0 1 1 1
    DT 09,2F,60 ; 040 199.5 * 1 0 1 0 0 0
    DT 07,82,70 ; 041 203.5 1 0 1 0 0 1
    DT 07,76,70 ; 042 206.5 * 1 0 1 0 1 0
    DT 07,66,70 ; 043 210.7 1 0 1 0 1 1
    DT 07,6F,6A ; 044 218.1 1 0 1 1 0 0
    DT 06,0xA3,70 ; 045 225.7 1 0 1 1 0 1
    DT 06,98,70 ; 046 229.1 * 1 0 1 1 1 0
    DT 06,8A,70 ; 047 233.6 1 0 1 1 1 1
    DT 06,72,70 ; 048 241.8 1 1 0 0 0 0
    DT 04,0xC3,99 ; 049 250.3 1 1 0 0 0 1
    DT 04,0xB9,99 ; 050 254.1 * 1 1 0 0 1 0
    DT 05,1C,99 ; 051 255 * 1 1 0 0 1 1
    DT 03,15,20 ; 052 1750 Eu Tone 1 1 0 1 0 0
    DT 05,0F,10 ; 053 1800 Eu Tone 1 1 0 1 0 1
    DT 01,84,9D ; 054 1200 Packet 1 1 0 1 1 0
    DT 02,13,30 ; 055 2200 Packet 1 1 0 1 1 1
    DT 03,26,50 ; 056 800 * 1 1 1 0 0 0
    DT 03,0F,50 ; 057 900 * 1 1 1 0 0 1
    DT 02,3F,50 ; 058 1100 * 1 1 1 0 1 0
    DT 03,36,20 ; 059 1300 * 1 1 1 0 1 1
    DT 01,68,20 ; 060 1500 * 1 1 1 1 0 0
    DT 03,09,20 ; 061 2000 * 1 1 1 1 0 1
    DT 02,1A,20 ; 062 2500 * 1 1 1 1 1 0
    DT 02,07,20 ; 063 3500 * 1 1 1 1 1 1
    ;
    ; * Indicates non EIA standard tone
    ;
    ; ORG 2100H
    ; DE "TonyHunt VK5AH CTCSSENC v 1.4 "
    END


    All CTCSS tones are within EIA standard of .08% .
    Use a 4Mhz crystal with 2x18pF capacitors.
    PTT line is active LOW. PTT is RB7 Pin 13.
    OUTPUT tone is on RA2 Pin1 ,see Low pass filter diag.
    Lines RB0-RB5 can be fitted with DIP switches to set
    tone frequencies as per table above. A 1 on the table
    indicates the RB pin is logic HI . All RB port pins have
    been programmed with internal pullup resistors and will
    float HI if left open. The binary inputs are read only on
    power up and not each time the PTT is keyed.

    For CTCSS tones use a Low pass filter as shown here as the
    output waveform is square. RO is an padding resistor to
    allow for level adjustment typically 20k.


    RA2--------2k2----------RO----Output
    Pin1 |
    |
    1uF
    |
    GND
     
  2. Brute

    Brute New Member

    Joined:
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    it gives:

    CORE-E0001: Stack over flow error occurred from instruction at 0x0000f0

    while simulating, is that a problem?
     
  3. be80be

    be80be Well-Known Member

    Joined:
    Aug 23, 2008
    Messages:
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    Location:
    morristown,tn
    Here you go brother I was right about the tables but over writing the main
    Code (text):


         LIST P=16C710
        #include <p16c710.inc>
        __CONFIG 3FF9H ;XTAL OSC @4Mhz,NO WATCHDOG,PWRRST,NO CP.
            __IDLOCS 1234
            ERRORLEVEL -302
    ;    
    CNT1    EQU 0CH ;PRESCALLER COUNTER REG 1
    CNT2    EQU 0DH ;PRESCALLER COUNTER REG 2
    CNT3    EQU 0EH ;PRESCALLER COUNTER REG 3
    TONREG  EQU 0FH ;REGISTER FOR TONE NUMBER
    PRES1   EQU 10H ;PRESCALLER STORE 1
    PRES2   EQU 11H ;PRESCALLER STORE 2
    PRES3   EQU 12H ;PRESCALLER STORE 3
    PORTA   EQU 5
    PORTB   EQU 6
    TRISA   EQU 85H
    TRISB   EQU 86H
    OPTREG  EQU 81H
    PC  EQU 2
    PULLUP  EQU 7
    STATUS  EQU 3
    INTCON  EQU 0BH
    GIE EQU 7
    RBIE    EQU 3
    RBIF    EQU 0
    RP0 EQU 5
    OUT EQU 2
    PTT     EQU 7
    ;  

        ORG     0x000
        GOTO    START
        ORG     0x004
    START
        banksel ADCON0
        clrf    ADCON0   ; DISABLE ADC
        movlw  0x3
        banksel ADCON1
        movwf   ADCON1
        ;
        BSF STATUS,RP0  ;SELECT REG BANK 1
        BSF     TRISB,PTT   ;SETUP RB7 AS INPUT FOR PTT
        BCF TRISA,OUT   ;SETUP RA2 AS OUTPUT FOR TONE
        BCF OPTREG,PULLUP   ;SET PULLUP RESISTORS ON PORTB
        MOVLW   0xFF     ; SET PORTB AS I/Ps
        MOVWF   TRISB    ; RB0-RB5 FOR SWITCH INPUTS

       
       

        BCF STATUS,RP0  ;SELECT REG BANK 0
        BCF INTCON,GIE  ;DISABLE GIE INTERUPTS
        BSF INTCON,RBIE ;ENABLE PORT B CHANGE INTERUPT
        MOVF    TRISB,W  ;READ DIP SWITCHES INTO W
        MOVWF   TONREG   ;STORE IN 0F REG
        BCF TONREG,6    ; CLEAR BITS 6&7 AS
        BCF TONREG,7    ; THEY ARE IRRELAVANTS
        MOVF    TONREG,W    ;RE-STORE INTO W
        ADDWF   TONREG,F    ; MULTIPLY BY 3
        ADDWF   TONREG,F    ; FOR TONE TABLE OFFSET
        ;
        MOVF    TONREG,W    ;RELOAD TO W FOR OFFSET
        CALL    TONTBL   ;GOTO TONE LOOKUP TABLE
        MOVWF   PRES1    ;STORE FIRST VALUE FROM TABLE
        ;
        INCF    TONREG,F    ;INCREMENT FOR NEXT TABLE VALUE
        MOVF    TONREG,W    ;RELOAD W FOR OFFSET
        CALL    TONTBL   ;GOTO TONE LOOKUP TABLE
        MOVWF   PRES2    ;STORE SECOND VALUE FROM TABLE
        ;
        INCF    TONREG,F    ;INCREMENT FOR NEXT TABLE VALUE
        MOVF    TONREG,W    ;RELOAD W FOR OFFSET
        CALL    TONTBL   ;GOTO TONE LOOKUP TABLE
        MOVWF   PRES3    ;STORE THIRD VALUE FROM TABLE
        ;
        ;
    RELOAD
        MOVF    PRES1,W  ;LOAD W WITH PRESET FOR 1
        MOVWF   CNT1     ;PRELOAD PRESCALLER 1
        MOVF    PRES2,W  ;LOAD W WITH PRESET FOR 3
        MOVWF   CNT3     ;PRELOAD PRESCALLER 3
        MOVF    PRES3,W  ;LOAD W WITH PRESET FOR 2 READY
    PTTCHK
        BTFSC   PORTB,PTT   ;TEST PTT LINE
        GOTO    WAIT     ;SLEEP TILL LOW
        CALL    CHORUS   ;DO DIVIDER/PRESCALLER ROUTINE
        ;
        OUTPUT
        BTFSS   PORTA,OUT   ;TEST O/P HI OR LO AT PRESENT
        GOTO    HI   ;IF LO GO SET HI
        GOTO    LO   ;IF HI GO SET LO
        ;
    HI
        NOP  ;BALANCE OUT CYCLE TIME MARK&SPACE
        BSF PORTA,OUT   ;MAKE O/P HI
        GOTO    RELOAD   ;RETURN TO START OF CYCLE
        ;
    LO
        BCF PORTA,OUT   ;MAKE O/P LO
        GOTO    RELOAD   ;RETURN TO START OF CYCLE
        ;
    CHORUS
        PRE1   
        DECFSZ  CNT1,F   ;DECREMENT PRESCALLER 1
        GOTO    PRE2
        GOTO    FINE     ;CALL FINE ADJUST SUBROUTINE
    PRE2    MOVWF   CNT2     ;RELOAD PRESCALLER 2
        ;
    PREE    DECFSZ CNT2,F    ;DECREMENT PRESCALLER 2   
        GOTO    PREE     ;GO BACK AND DECREMENT PRE2 TILL 00
        ;
        GOTO    PRE1     ;GO BACK AND DECREMENT PRE1 TILL 00
        ;
    FINE    DECFSZ  CNT3,F   ;DECREMENT PRESCALLER 3
        GOTO    FINE     ;GO BACK AND DECREMENT PRE3 TILL 00
        RETURN   ;RETURN TO CHANGE O/P AND CHECK PTT ETC
    ;
    WAIT
        BCF INTCON,RBIF ;CLEAR PORT B CHANGE INT FLAG
        SLEEP    ;SLEEP AND WAIT FOR PTT
        NOP
        BCF INTCON,GIE  ;DISABLE GLOBAL INTERUPTS AGAIN
        GOTO    PTTCHK   ;CHECK IF PTT PASSES TEST
        ;
        ;
        ;
        ;TONES TABLE AT 0008H
    ;   ORG 0007H
        TONTBL
        ADDWF   PC,F     ; W+PC ->PC, JUMP DOWN TABLE
        ;
        ;
        ;    16c710 PIN
        ; 11 10 9 8 7 6
        ;    TONE FREQ RB5 RB4 RB3 RB2 RB1 RB0
        ;
        DT  02,01,0x9D  ; 000 1Khz TEST 0 0 0 0 0 0
        DT  86,82,10    ; 001 67.0 0 0 0 0 0 1
        DT  81,85,10    ; 002 69.4 * 0 0 0 0 1 0
        DT  84,80,0x0F  ; 003 71.9 0 0 0 0 1 1
        DT  7F,85,0x0F ; 004 74.4 0 0 0 1 0 0
        DT  7B,7C,0x0F  ; 005 77.0 0 0 0 1 0 1
        DT  76,86,0x0F  ; 006 79.7 0 0 0 1 1 0
        DT  72,82,0x0F  ; 007 82.5   0 0 0 1 1 1
        DT  74,8F,0x0E  ; 008 85.4   0 0 1 0 0 0
        DT  63,91,10    ; 009 88.5   0 0 1 0 0 1
        DT  5F,9A,10    ; 010 91.5   0 0 1 0 1 0
        DT  5B,47,11    ; 011 94.8   0 0 1 0 1 1
        DT  55,88,11    ; 012 97.4   0 0 1 1 0 0
        DT  56,49,11    ; 013 100.0  0 0 1 1 0 1
        DT  09,6E,0xB9 ; 014 103.5   0 0 1 1 1 0
        DT  08,81,0xC9  ; 015 107.2  0 0 1 1 1 1
        DT  0A,71,98    ; 016 110.9  0 1 0 0 0 0
        DT  0B,76,83    ; 017 114.8  0 1 0 0 0 1
        DT  0A,0xCA,83  ; 018 118.8  0 1 0 0 1 0
        DT  0A,9A,83    ; 019 123.0  0 1 0 0 1 1
        DT  09,0xF1,83  ; 020 127.3  0 1 0 1 0 0
        DT  08,93,9D    ; 021 131.8  0 1 0 1 0 1
        DT  07,94,0xB0  ; 022 136.5  0 1 0 1 1 0
        DT  07,7C,0xAD  ; 023 141.3 0 1 0 1 1 1
        DT  07,85,0xA5  ; 024 146.2 0 1 1 0 0 0
        DT  08,7B,89    ; 025 151.4 0 1 1 0 0 1
        DT  08,80,83    ; 026 156.7 0 1 1 0 1 0
        DT  07,0xA2,90  ; 027 159.8 * 0 1 1 0 1 1
            DT  08,47,86    ; 028 162.2 0 1 1 1 0 0
        DT  07,60,95    ; 029 165.5 * 0 1 1 1 0 1
        DT  08,86,78    ; 030 167.9 0 1 1 1 1 0
        DT  07,92,87    ; 031 171.3 * 0 1 1 1 1 1
        DT  07,90,85    ; 032 173.8 1 0 0 0 0 0
        DT  07,7D,85    ; 033 177.3 * 1 0 0 0 0 1
        DT  09,5A,66    ; 034 179.9 1 0 0 0 1 0
        DT  09,48,66    ; 035 183.5 * 1 0 0 0 1 1
        DT  07,9E,78    ; 036 186.2 1 0 0 1 0 0
        DT  08,0xBB,60  ; 037 189.9 * 1 0 0 1 0 1
        DT  09,4C,60    ; 038 192.8 1 0 0 1 1 0
        DT  08,9D,60    ; 039 196.6 * 1 0 0 1 1 1
        DT  09,2F,60    ; 040 199.5 * 1 0 1 0 0 0
        DT  07,82,70    ; 041 203.5 1 0 1 0 0 1
        DT  07,76,70    ; 042 206.5 * 1 0 1 0 1 0
        DT  07,66,70    ; 043 210.7 1 0 1 0 1 1
        DT  07,6F,6A    ; 044 218.1 1 0 1 1 0 0
        DT  06,0xA3,70  ; 045 225.7 1 0 1 1 0 1
        DT  06,98,70    ; 046 229.1 * 1 0 1 1 1 0
        DT  06,8A,70    ; 047 233.6 1 0 1 1 1 1
        DT  06,72,70    ; 048 241.8 1 1 0 0 0 0
        DT  04,0xC3,99  ; 049 250.3 1 1 0 0 0 1
        DT  04,0xB9,99  ; 050 254.1 * 1 1 0 0 1 0
        DT  05,1C,99    ; 051 255 * 1 1 0 0 1 1
        DT  03,15,20    ; 052 1750 Eu Tone 1 1 0 1 0 0
        DT  05,0F,10    ; 053 1800 Eu Tone 1 1 0 1 0 1
        DT  01,84,9D    ; 054 1200 Packet 1 1 0 1 1 0
        DT  02,13,30    ; 055 2200 Packet 1 1 0 1 1 1
        DT  03,26,50    ; 056 800 * 1 1 1 0 0 0
        DT  03,0F,50    ; 057 900 * 1 1 1 0 0 1
        DT  02,3F,50    ; 058 1100 * 1 1 1 0 1 0
        DT  03,36,20    ; 059 1300 * 1 1 1 0 1 1
        DT  01,68,20    ; 060 1500 * 1 1 1 1 0 0
        DT  03,09,20    ; 061 2000 * 1 1 1 1 0 1
        DT  02,1A,20    ; 062 2500 * 1 1 1 1 1 0
        DT  02,07,20    ; 063 3500 * 1 1 1 1 1 1
        ;
        ;    * Indicates non EIA standard tone
            ;

        END


    All CTCSS tones are within EIA standard of .08% .
    Use a 4Mhz crystal with 2x18pF capacitors.
    PTT line is active LOW. PTT is RB7 Pin 13.
    OUTPUT tone is on RA2 Pin1 ,see Low pass filter diag.
    Lines RB0-RB5 can be fitted with DIP switches to set
    tone frequencies as per table above. A 1 on the table
    indicates the RB pin is logic HI . All RB port pins have
    been programmed with internal pullup resistors and will
    float HI if left open. The binary inputs are read only on
    power up and not each time the PTT is keyed.

    For CTCSS tones use a Low pass filter as shown here as the
    output waveform is square. RO is an padding resistor to
    allow for level adjustment typically 20k.


    RA2--------2k2----------RO----Output
    Pin1     |
    |
    1uF
    |
    GND
     
    This code should run fine here the hex if you want it
     
  4. dave

    Dave New Member

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  5. Brute

    Brute New Member

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    You think this will puke out tone at RA2? You think the hex will work instantly? Hope so will try, let you know, TNX!
     
  6. be80be

    be80be Well-Known Member

    Joined:
    Aug 23, 2008
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    Location:
    morristown,tn
    You compile the code a absolute code
    View attachment 68677


    Have a look here you can now see the pins set should work the code ran and looked like it was doing what you want

    Well I could be wrong but the code in mplabsim was jumping over the main and starting at the table code part.

    so none of your setup code was run.
     
    Last edited: Nov 16, 2012
  7. Brute

    Brute New Member

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    Thanks bro, I will compile and test and let you know, TNX!
     
  8. atferrari

    atferrari Well-Known Member

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    Simulate and watch ALL registers

    What test is that? In the actual chip? Or just a simulation?

    I just come from adapting some code for a 18F452 to a 18F4520 and it took me no more than 4 hours. Almost three to actually print the manual (Epson T25 - double face) for future use and less than one to find a mistake that was in freshly writen code (simply found by simulation).

    Those steps I outlined somewhere before, I followed them verbatim so I knew the bug was in the new code.

    Additional suggestion: open a "Watch" window" and put in there ALL the GPR registers used by your code.

    It is simple to know which one has changed after each step. Just look for those in red. That should tell you if something is going off the expected path.

    I do not know if this even could be your case but that horrible banking could make you changing NOT the desired register but something else.

    My experience: CONFIG options for a simple "Hellow word" or "blink a LED" start, that have ON/OFF alternatives can be safely set to OFF. Another way to look at it, Brute. I honestly expect some EE or programmers to contend on this. Oh, yes.

    ¡Buena suerte! Yes, good luck!
     
    Last edited: Nov 17, 2012
  9. be80be

    be80be Well-Known Member

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    You don't really get to do a blinky on a 16C chip now I'm don't no for sure what I did fixed it but the code was running top down.
    Where as his code jumped over the main setup code and stayed in the table part of the code.

    But in mplabsim the code after some changes showed the register's show the values that the code has in it so it should work

    The 16C710 is a smaller chip 512 not a 1k as the 16c84 and the goto 0008C put the table stuff in the main part of the code.
     
    Last edited: Nov 17, 2012
  10. Brute

    Brute New Member

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    Hey Burt, finally it works! I've been programming and testing it today because I was away in the weekend but man you helped me a lot with this!
    Thanks very much Burt, Ian and all involved in this thread!
     

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