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How do I memory mapp LCD with 8051

Discussion in '8051/8951' started by vik1501, Nov 19, 2003.

  1. vik1501

    vik1501 New Member

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    It will be nice if somebody could provide me with tried & tested scheme/hints/URLs/books/articles.....etc for memory mapping of LCD with 8051 based microprocessor

    I have tried my best but could not get an LCD work :( may be because of timing requirements of various pins like enable ( pin 6 ), data set up (7 thro' 14) , RS & R/W and the 8051 memory write cycle timing conflict. :roll:

    thanks in advance !!
     
  2. kinjalgp

    kinjalgp Active Member

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    The E signal is an active high enable, which should be asserted when the processor makes a access to the LCD. RS and R/W are control lines for the display. In order to meet the timing requirements these should remain asserted and stable while E is also asserted.


    Check this design. It works. I have tested it personally.
    http://www.pjrc.com/tech/8051/board4/schematic.html

    LCD available at:
    FE00 WR Only Command Register
    FE01 RD Only Status Register
    FE02 WR Only Display or CGRAM Buffer
    FE03 RD Only
     
  3. vik1501

    vik1501 New Member

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    Confusion prevails 87C52 NE 89C55WD pin for pin

    Thanks for the reply kinjalgp !
    :D

    But I am using 89c55wd from atmel. And it doesn't seem to be pin to pin compatible with 87C52. or is it package dependent ? I am using DIP package IC.


    Final words - Birth of Twins is not frequent but still Natural
    for kinjalgp with luv
     
  4. dave

    Dave New Member

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  5. kinjalgp

    kinjalgp Active Member

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    Majority of 40 Pin variants of 8051/52 are pin compatible. Check it out once more.

    My words for you (not final) - Killing (deleting) one of the twin on this board is my duty and I really hate that. So I request you to kindly stop giving birth to twins as far as possible. It causes message (poplulation) explosion on the board. :wink:
    - Moderator @ www.electro-tech-online.com

    Hope you got my point :)
     
  6. vik1501

    vik1501 New Member

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    Dear Kinjalgp,

    Plz check [url]http://www.pjrc.com/tech/8051/board4/schematic.html [/url], the site suggested by you.

    I am confused about the connections shows.

    e.g. D0 = P0.0 is named as D3 when connected to D0 of 74HC373 and same problem with other connections :(

    I just want to check the LCD logic first before employing the rest of the scheme.

    But then how this scheme will work :?:

    Plz explain
     
  7. kinjalgp

    kinjalgp Active Member

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    Yes you will find that because the guy (Paul) has purposely done that to make PCB design easy. It doesn't matter in what order you connect the address lines to the RAM/ROM. It will only change the physical address of the data inside the memory. If you want you can connect it in proper way. It won't affect the circuits working.

    Read this note given at the bottom of the same page that I suggested you.
    "This unusual address bus wiring works. The 74HC373 chip (U2) is 8 identical flip-flops, so it does not matter which one is used for each line. On the RAM (U3) and Flash ROM (U4) chips, all data that is stored in these chips is written by the 87C52 chip (U1), so it does not matter which physical location within the chip is mapped into each location within the CPU's address space, because each read from these chips will return the same data that was written from a previous write."
     
  8. vik1501

    vik1501 New Member

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    :D
    Thanks ! Kinjalgp

    I have taken up the work. First I will ONLY check the LCD logic and am sure it will work. Your view & reviews give me a lot of confidence. :p


    Regards
     

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