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Hold High

Discussion in 'Electronic Projects Design/Ideas/Reviews' started by Quercus, Aug 17, 2017.

  1. Quercus

    Quercus New Member

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    Hello,

    I need hold a logic state high, once achieved, until I intentionally change it, even if the initiating high reverts to low.

    I'm using a CD4060 timer to put a circuit into low-power standby state. An idle circuit allows the timer to advance, and after about 20 minutes the Q14 pin goes high opening the power relay and de-energizing the power circuit (the standby/timer circuit retains power, of course). However, the timer will continue to advance indefinitely, and after another 20 minutes, Q14 will return to low and the power circuit will re-energize. I need to maintain the logic high initiated by Q14 until I intentionally change it.

    At the moment, I'm considering a latching relay. Other thoughts/better ideas?

    Thanks,
    -Quercus
     
  2. MikeMl

    MikeMl Well-Known Member Most Helpful Member

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    How about a "latch"?
     
  3. dr pepper

    dr pepper Well-Known Member

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    Similar thing with a different Ic, a 4013 D type flip flop, ground the clock, and D inputs and use the set and reset inputs.
     
  4. dave

    Dave New Member

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  5. ci139

    ci139 Active Member

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    in designing the digital control there are multiple . . . ?features to constantly keep track on -- some of which are
    • blah ... (ok i got the bullets here)
    • superimposed/simultaneous (control-)events that conflict in defining system advance/state
      -- both control signals may be needed but in special ?conditional arrangement e.g. some sort of priorised.fnOf(?) setup
    • the polarity of the "master" ()general/global control signals . . . versus latching edges(leading trailing)
      -- say , there might be many state-changes tied to a ?"Master Sync." pulseĀ“s leading edge ++and they are time critical e.g. *if the complementary pulse - (required) for/by some of the modules - is formed locally (inverter) then that module gets off sync. due timing difference of the complemented clock *if ends
      -- say the 2-nd , if** you start changing (playing around with) the polarity/edges of control signals - then each such change may require a re-make/-design of the entire!!! existing circuitry . . . if** ends
    • blah . . .
    shortly instead of setting ever higher resolution to a Control Clock (as a last measure) the tedious alternative is to witch out the control "pulse" from existing transitions of the logic lines . . . either by basic logic gates , flops , delay circuits , transmission/-pass gate , e.c. - e.g. there are likely too many solutions to your problem
     

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