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ESD Protection Diodes for ARM Processor?

Discussion in 'ARM' started by MrAl, Oct 31, 2015.

  1. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hello there,

    SAM 3X8E

    I checked the data sheet but could not find information regarding the ESD protection diodes normally found on microcontroller input/output lines.

    For example, with the Atmel 328P chip they show a diagram with the two diodes on the input of each pin, and same for PIC chips.
    They also give the current rating for the diodes typically 20ma.
    With the ARM chip however, it does not seem to show anything about this nor even talk about it on the data sheet. It is unlikely that they dont have any, but I need to know this for sure, and hopefully what the current rating is.

    Thanks.
     
  2. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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  3. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi Tony,

    Did you find something in that link that talked about the diode clamps on the i/o pins?
    I could not seem to find anything in that link.
     
  4. dave

    Dave New Member

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  5. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    Electrostatic Discharge (ESD) protection is provided by 4 pnls per side:

    No details but there are ESD standards ... (ref NXP)
    In accordance with the Absolute Maximum Rating System (IEC 60134).

    Per diode
    Ppp peak pulse power t p = 8/20 µs 16 W max
    Ipp peak pulse current t p = 8/20 µs 1.5 A max
    Vesd electrostatic discharge voltage Tr <1 ns, PW50= 60 ns
    IEC 61000-4-2 (contact discharge) 12 kV ( required >8kV on contact)
    MIL-STD-883 (human body model) . 10 kV ( required >4kV)

    - - - - - -
    This imples Vf= 7.11 Ω @1.5A for ESR above Schottky Vth threshold voltage that reaches 12.67V @ 1.5A.. From my experience ESR or differential resistance at 1mA ~ 200 Ω which implies 5mW max. continuous. ( ESR~=1/Pd continuous ... my rule)
     
  6. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi Tony,

    Thanks. What does "pnls" mean in the first line?

    So here is the test circuit...

    ARM processor running normally, 3.3v main power supply so output pins will normally output close to 3.3v for a logic high.
    A resistor connected to a pin configured as an INPUT pin, the other end of the resistor going to +5v.
    This of course means that if there was no internal clamp diode going from the pin to +3.3v the pin would be subjected to the full +5v supply through the current limiting resistor. The current is continuous because both supplies are constant.
    With this setup, what would you say would be the maximum input current through the clamp diode assuming no other diodes were conducting?
    The current into the pin would be (5-3.3)/R=1.7/R, so a little table for several values of R:
    1 ohm, 1.7 amps
    10 ohms, 0.17 amps
    100 ohms, 0.017 amps
    200 ohms, 0.009 amps approximate
    300 ohms, 0.006 amps approximate
    500 ohms, 0.0034 amps
    1000 ohms, 0.0017 amps
    2000 ohms, 0.0009 amps approximate

    Do you think the 300 ohms resistor would be enough to protect the internal diode, or do you think we'd really need something like 2k to achieve that protection?

    What i am trying to do is establish what would be an acceptable series current limiting resistor for use with a +5v external system connection, in the event of a full 5v signal reaching the other end of the resistor (only protection then is the diode).

    With many of the PIC chips, we see this right in the specs for the diodes in the data sheet, and they specify 20ma max. With this ARM chip they make it much more difficult to figure out exactly how much the diodes can take. In particular the upper diode clamp to +3.3v as the lower one to ground should never have to conduct under normal or the expected fault conditions.
     
  7. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    The purpose of internal ESD-protection diodes is self explanatory and logarithmic in nature, but can be linearized for static DC in your example using the incremental resistance or ESR as I call it. I know that the ESR is inverse to the rated steady state power of all diodes. In this case it is a very fast low capacitance diode, much faster than the devices to clamp very fast , transmission line pulses (VF-TLP), it must be limited in steady state power.

    to limit the current between 5.5V and 3V using a 10% worst case tolerance difference of 2.5V across a Schottky diode which has a 0.15V threshold and an incremental resistance or ESR at rated power on the order of 15mW but a much higher J rating in the SOA limits of the diode. The trick is that the protection diode must clamp faster than the embedded PNPN SCR effect can respond at 0.65V even though the voltage may in fact greatly exceed 0.7V for many nanoseconds with a 4kV VF-TLP. This is due to the impedance ratio at TLP speeds of the diode vs the substrate capacitance of the PNPN junction in CMOS, which is largely undocumented.

    Therefore I would suggest to use 15 mW for the internal CMOS ESD diodes and 1/15mW= ESR of 66 Ohms for the series resistance for DC from the external %V source. THus 2.5V worst case drop into 0.3V the absolute maximum of the CMOS specs is 2.2V difference with 15mW/0.3V= 50mA as the absolute maximum for DC. Therefore the protection R you may use for 5.0V*110% to 3.3V*90% +0.3Vd clipping must be greater than (5.5-3.3V)/50mA=44 Ohms. I would suggest 50 ~100 minimum, unless a lot of lines are interfaced this way with Pd accumulation)

    I accept there is no documentation from ARM on the ESD protection diodes and only that it satisfies the IEC ESD standard.
    My conclusions above are solely based on my experience with all diodes that seem to follow the incremental ESR <= 1/ Pd where Pd is the static power rating of any diode at 85'C. I have found this to be true from 0.5/Pd ~ 1/Pd for every diode VI curve I have analyzed from LED's to 1000A power diodes. THis also explains all the variations of Vf tolerances for all single LED's ( not strings or arrays of LEDs, where equivalent network ESR must be computed)

    I also know that all ARM CMOS devices use ALVC2 type CMOS drivers for outputs with 25 Ohm ESR as opposed to LV CMOS drivers with 50 Ohms and HCMOS drivers with 200~300 OHm ESR driver impedance, so I expect the protection diodes to be as low as possible without compromising the input capacitance and speed if the logic level interface.

    You may get a completely different response from ARM tech support, but I have found my experience tells me what I have written.

    For more info on ESD protection, but not what you are looking for ....
    https://www.google.ca/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0CB0QFjAAahUKEwjLzoOMmfLIAhXFkx4KHRj4B3E&url=http://www.infineon.com/dgdl/AN210_v1_3.pdf?fileId=db3a30432cd42ee3012cee8d005b0c19&usg=AFQjCNFfDCGdtd5FuhIYx2zM7xOO8LgStg&sig2=S_MnkmSnGpXVca3KhxnfYQ << excellent
    http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=tpd5s116&fileType=pdf

    CONCLUSION

    Yes 300 Ω is adequate.
     
    Last edited: Nov 2, 2015
  8. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hello again Tony,

    Thanks for the info.

    I have also read now that someone connected a 4.7k resistor from the +5v line to one of the i/o pins, and reported that there was no clamping action. So the pin measured +5v.
    Unfortunately i dont have any other details, such as did the diode blow out during some other test.

    For me to test this i would have to apply 3.3v with maybe a potentiometer voltage divider and maybe 1k pin series resistor, then slowly raise the pot voltage until i see (or dont see) any clamping action at the pin itself. I just fear that this could damage the chip. They do spec 4.0 volt max though.

    BTW, some of these i/o pins have a normal max sourcing rating of 3ma, which is much lower than the typical uC like the Atmel 328P or the low end PIC chips.
     
  9. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    Maybe they blew the diode open.
    Or maybe you will discover ARM has no ESD protection to get better speed.
     
  10. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi,

    Yeah that would be totally nasty. Maybe that is why they dont show them on the data sheet :)

    BTW, just so we are all on the same page, i am including a drawing of the circuit with the ESD protection diodes, if they are really present.
     

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  11. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    If in doubt it is better to add protection than ask for forgiveness. Have you considered power up sequence issues etc?

    There are many ARM driver types with recommended series clamp resistor recommended for optimal clamping overshoot . The highest current drivers are also the fastest which use the smallest recommended Series R on the order of 15 Ohms for a 30mA driver . ( forgot link) Also Current rating of driver is only for RdsOn Vol, Voh specs, not actual limit current.

    All the detailed datasheets , I believe are available for registered users.
     
    Last edited: Nov 2, 2015
  12. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    I guess for external transients beyond handling of the chip, the TMOV's and VS solutions are recommended.
    http://www.eetimes.com/author.asp?doc_id=1321263&page_number=2
    "Surge and ESD protection is not the same"

    https://www.speed2design.com/the-shocking-truth-about-static-discharge-dangers/

    I recall in 1982 when we have a home trial of an integrated services digital network with our set-top box on the TV with payTV, alarms, digital voice, teleshopping and 1.544Mbps 2way to 100 homes and in the winter, touching the TV would transmit an ESD pulse to the motherboard in the basement, all using CMOS at the time of course. THe slight odor of hot epoxy from the CMOS driver chip could be extinguished by resetting the power due to the SCR latchup effect. Even though we had ESD protection, the ground were too inductive and ground shift caused the latchup effect, which was resolved within a few days. We were using HCMOS at the time which has a higher ESR, the fault was cleared with power cycling, but with LV CMOS with lower ESR, the latchup is usually catastrophic from shootthru. across the Vcc<>Vdd with the PNPN junction in the substrate.

    Our solution was to add a common mode choke to the RJ-11 port and improve case ground

    I'm pretty sure ARM has protection diodes of different types for each interface pin
    "Electrostatic Discharge (ESD) protection is provided by 4 pnls per side:".
    I think this refers to the embedded custom design of the substrates for Schottky pn junctions.
     
    Last edited: Nov 2, 2015
  13. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi again Tony,

    Hey thanks for looking into this. They made it extra difficult to find this information out for some reason.
    Yeah i was seeing that external addition information too, about adding our own protection diodes/IC with diodes or other protection devices. I could add my own diode and i most likely will anyway, but it would be nice to see some real data that shows what the pin can really take. Geeze, all the other uC chips i have worked with in the past had this information readily available on the data sheet.
    Another area of application is when interfacing with the ADC pins with an analog voltage. If the external impedance is made high enough (voltage divider resistors for scaling) the input is automatically protected for reasonable over voltage inputs to the divider as long as the upper ESD diode can conduct that tiny current. If there is really no diode that's a problem though. As you found though, there most likely is a set of diodes like most other chips, although they may have a lower current rating.

    Unfortunately i can not query that user that did the 4.7k current limiting resistor experiment either, all i can do is try to reproduce it myself. I have a feeling something wasnt done right for that test though so i will probably find that there is some clamping action. I hope the chip survives though because although i can do some SMD rework this chip has 144 pins and they are spaced at an extremely small pitch.
    I guess the worst that could happen is the pin will get all the way up to 4.0 volts with no current flowing through the series resistor.
     
  14. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    With the DMM diode test mode, you can probe bumps wrt. Vcc,Vdd and verify 0.2V on all inputs. Further to this if you apply 1.5V with a 1K then 2K , measuring current, you can compute the incremental R or Series ESR of the diode using 5~10mA.

    DMM's typically use around 1mA CC to measure Vf, shown on the LCD during diode test mode then display numbers which are actually mV up to the display resolution of typically 3 1/2 digits or 3V or similar.
     
    Last edited: Nov 2, 2015
  15. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi,

    Well, keep in mind that we are still dealing with the possibly unknown, where there may be no diode or something. That means i dont think i would trust using a meter to measure this, just a well thought out test with well defined parameter settings.
    I was even thinking that 5v is too high for the pot power line, because for one thing noise on the arm could cause 5v to appear on the wiper terminal temporarily. Lowering to 4v would be better i think for the initial test, then if that goes well then back up to +5v because that will be the real life external source to the 5v circuitry.

    What a pain this new 3.3v standard brings.
     
  16. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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  17. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi Tony,

    That link points to a "Series Termination" note, so i guess you are implying that there must be clamp diodes then for that note to work?
    If you state your intention with the links and notes it will be easier for me to understand what you are trying to say.
    Thanks :)
     
  18. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    I think any CMOS chip these days that is ESD compliant ( as are ARM's chips ) will have diodes to each rail Vss,Vdd.
    The link shows what to expect and the 0.3V outside the rails is the diode Vf at rated current ( probably 5 mA)
     
  19. MikeMl

    MikeMl Well-Known Member Most Helpful Member

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  20. MrAl

    MrAl Well-Known Member Most Helpful Member

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    Hi again,

    Tony:
    Yes i think that is true, and i will find out for sure soon :)

    Mike:
    Thanks for the link. That looks interesting too.
    I have to think economics too though, as i might have up to 75 pins to 'protect' :)
     
  21. Tony Stewart

    Tony Stewart Well-Known Member Most Helpful Member

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    If you want to ask the Manager of ESD design for ARM, you can ask him directly why their data is so much hidden. He came with lots of experience and has been the ESD manager since.,
    [​IMG]
    Fabrice Blanc

    Principal ESD Design Engineer at ARM

    France
    Semiconductors
    Current Principal ESD Design Engineer at ARM Embedded Technologies
    Past ESD Design Support at NXP semiconductors, ESD expert at Philips Semiconductors in Zürich, ESD expert at Philips Semiconductors in...
    Education Institut national des Sciences appliquées de Lyon, Institut national des Sciences appliquées de Lyon, Université Joseph...
    Summary IC design support for ESD and latch-up immunity
     

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