Delaying digital signal (frequency dividing)

[onder]

Hi there,
I need to make serial to parallel conversion using shift registers.
I will be sending serial data to drive 7 seg displays.
I am to convert serial data to parallel using several shift registers and from then I can use 4511 bcd decoder to run the 7 segs.

My problem is in creating the clock signal for the shift registers. I tried 555 in astable mode to run twice the frequency as my data then invert the output to get rising edge clock signal. Synchronization is a big pain, system runs whenever if feels fine, fails otherwise.

My current approach is to use the data as my clock. My data rate is very slow (10 ms for each bit). I will give an example: If I want to send a bit zero, I will send a zero for 3 ms, a one in between 3-4 ms and back to zero in between 4-10. (10 ms eachbit)

If I can delay my data by 3 ms and tie this to the clock pin of my shift register, then my rising edge clock will happen at 6th ms at which my data will safely be a zero, so I will be able to shift my data correctly. The only problem is to create the delay.

I will really appreciate if someone can help me in with this delay generation!!
Thank you

 

[crust]

In network communication and transmission, what you have is an encoding problem. There are many different solutions with varying levels of complexity and efficiency. For instance, you could use the falling edge of a signal to represent a 0 and the rising edge to represent a 1. Then your serial->parallel converter only has to look at the transitions. Another method is to use 4b/5b encoding. In this case, you represent a 4 bit sequence with 5 bits. This way you assure that you will never get a long string of 0s or 1s. You use the edges to synchronize your receivers clock.

 

[onder]

This is not a professional design. What i need to use are standard logic components. So I don't think that i can use a falling edge, rising edge serial to parallel converter.
I just need to delay my signal by 2 ms.
Thank you for the input though.

 

[Roff]

You shouldn't need much resolution in the delay, so you could do it digitally by clocking the data through a multi-bit shift register at an asynchronous higher clock rate. For example, an 8 bit SR clocked at 4kHz will give you a 2ms delay with 0.25ms resolution. If you need more resolution, lengthen the SR and raise the clock rate proportionally. The CD4006B is an 18 bit SR, but it may be hard to find.
There is a possible analog solution if your shortest pulse (1 or 0) is longer than the required delay. You can get the delay by passing the data through an analog slew rate limiter and a comparator. If this sounds interesting, I can show you how to do it. It will take more parts than the all-digital solution.