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3 - 10 MHz coil drive

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kellbengal

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Hi - first time posting to the forum, so please be gentle. :D

I'm trying to build a very compact circuit to drive a 10 nH coil via an H-bridge at 3 MHz. A very similar application requires the same thing at 10 MHz. Each circuit (including fets and a tiny PIC) has to fit into a 40x20 mm area (not counting the coil).

My first thought was to start with a 20-40 MHz oscillator, put it through a counter and then use some gates with an RC circuit to put in a deadzone where all the FETs would be off (to avoid large cross-over currents). However, this has turned out to be too bulky.

I think what I really need is a motor-drive IC, but I've not seen any that can handle anywhere close to 3 MHz, let alone 10 MHz.

Does anyone know of a suitable part, or have any suggestions? I'm just about ready to consider putting in a signal micro to drive the bloody FETs directly. Any thoughts?

Edit: I only need 3.3 v across the coil, so the FETs don't have to be fancy. There are no huge currents involved.
-Kell
 
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No, actually - I'm trying to build an induction charging system... although there are a number of similarities.

It would be nice if it was all in convenient RF frequencies because then there would be plenty of parts available. Instead, it falls in this awkward place between motor drives and RF.
 
How about a pair of comparators. The inductor connects between the outputs of the comparators and the inputs are connected so that when one comparator is ON the other is OFF. There are many comparators that operate at high frequencies. You may have to put good buffers after the comparators, if they cannot drive the inductor. L di/dt. A little experimentation may be necessary here.

Edit: The reactance of a 10nH coil at 3 MHz is so small, you can consider the coil to be a resistor, resistance determined by the wire in the coil. It's curious to me that you can accomplish any significant inductive coupling under those conditions.
 
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10nH is far too smaller inductance to work at 3MHz.
Presumably you'll need it to be tuned for optimal performance which would require a 280nF capacitor, 330nF being the nearest value. The problem is the capacitor will probably have a high enough inductance and a low Q (due to dielectric losses) that it won't be very a good capacitor at high frequencies.
 
Sorry for the late reply! I've just moved house and my time is being stolen by work and house things. Not nearly enough time left over to do more important electronics things.

To answer some questions, "huge" means an amp or more.

Yes, I get surprisingly good inductive coupling - on the bench I've had 90% coupling efficiency, driving the primary coil with a signal generator at 3 MHz.

The inductance of the coil I'm using was calculated using an online tool, not measured - maybe I put a number in wrong and it should be 100 nH, but it is a very tiny coil and 10 nH seemed intuitively correct to me. 3 MHz really is the optimal frequency (well, ok, it's really closer to 2.9 MHz) as tested with an RF sig gen and oscilloscope on the secondary coil.

The essential thing about this induction charging system is that it is intended for transferring only the merest smidgen of power.

The problem with simply using two comparators, I think, is that you won't get any period between waves where both sides of the H-bridge are "off".

I have a circuit which I've tested on the bench that sort of produced what I need, but with some problems. I keep getting some glitches on the output (see attached). I've got big capacitors on the supplies to all my chips, but I suspect there is something I'm missing - maybe a race condition?

Any thoughts?
 

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Before we go farther, what the hell is that 1uF cap to ground doing on the clock input?
 
Kell:

With opposing comparators you don't have the issue found with h-bridges related to the need for a dead-band to prevent all the transistors from turning on at once.

However, be aware that voltage glitches are inherent with switching any inductance with a fast switching risetime (like the edges of a square wave) as a change of current through an inductor is opposed by the generation of a voltage across the inductor proportional to the rate of change of the current and the inductance.

If a smooth drive is desired with no glitches, perhaps a sinusoidal oscillator/driver is the way to go. You did not state where you are measuring these glitches and why the glitches are a problem.
 
ccurtis - Good points and something I had not considered. The glitches are on the outputs that drive the fets - if they glitch at the wrong time, current will flow direct from power to ground, wasting precious battery power. Sinusoidal power is a possibility... I put a filter on the fet inputs and use them like an amplifier rather than a switch. It will require adding four components, but it might just work a treat.

Roff - another excellent point, and a consequence of making last minute changes to circuit diagrams that then don't reflect what you're actually doing. In the real circuit there is a gate between the clock and the filter - in my haste to produce a jpg to post I forgot to include it. Mea culpa.

I've attached the corrected circuit, now fortified with extra correctness.
 

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ccurtis - Good points and something I had not considered. The glitches are on the outputs that drive the fets - if they glitch at the wrong time, current will flow direct from power to ground, wasting precious battery power. Sinusoidal power is a possibility... I put a filter on the fet inputs and use them like an amplifier rather than a switch. It will require adding four components, but it might just work a treat.

Ron - another excellent point, and a consequence of making last minute changes to circuit diagrams that then don't reflect what you're actually doing. In the real circuit there is a gate between the clock and the filter - in my haste to produce a jpg to post I forgot to include it. Mea culpa.

I've attached the corrected circuit, now fortified with extra correctness.
Loading the output of a gate with a cap to achieve timing requirements is bad engineering. Perhaps you meant to put it on the other side of the resistor?
 
Even if your drive to the H-bridge has a dead band, there are limitations within the H-bridge on switching speed, such as gate capacitance that prevent one half of the H-bridge from being able to turn-off before the delayed turn-on of the other half.
 
Loading the output of a gate with a cap to achieve timing requirements is bad engineering. Perhaps you meant to put it on the other side of the resistor?

Yes, and if the cap is placed after the resistor to create a delay, putting the delay at the clock input isn't going to create a dead band. It would be placed after one of the outputs.
 
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Yes, and if the cap is placed after the resistor to create a delay, putting the delay at the clock input isn't going to create a dead band. It would be placed after one of the outputs.
The delay creates a short negative pulse at the clock input. When you AND that with the two flip-flop outputs, you do get a dead zone, but there needs to be a couple of inverters added between the clock input and the inputs to the AND gates, or he will get glitches due to the propagation delay of the flip-flop.
 
The delay creates a short negative pulse at the clock input. When you AND that with the two flip-flop outputs, you do get a dead zone, but there needs to be a couple of inverters added between the clock input and the inputs to the AND gates, or he will get glitches due to the propagation delay of the flip-flop.

Yes, I see that now. Only one of the gates will switch with the clock, depending on the state of the flop. The flip-flop switches after the output gates are clocked, causing a glitch.
 
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