I want to make you aware of a couple of interesting circuits I came across over the years. The file “LatchSync.JPG” shows a clip of the two circuits.
I found a simple logic simulator on the Internet at http://sourceforge.net/projects/cedarlogic/?source=dlp and used it to test the circuits described below. I you chose to download the free program and install it, you can load the design file “Latch and Sync Circuits.cdl” and try it yourself.
First is a transparent latch circuit that avoids a race condition called “a hazard” in the business. A transparent latch circuit is useful when designing with a PLA or FPGA and you have full control of the circuit topology. Although you can make a simpler latch by omitting the middle NAND gate, the circuit then depends on the propagation delays between the upper NAND gate and the lower NAND gate. A situation may occur where the latch “drops out” and produces an incorrect value. By including the middle NAND gate, this “race” condition is eliminated and the latch behaves as expected every time.
In 1971, or there about, Texas Instruments came out with an interesting TTL chip part number SN74120. It contained 2 independent pulse synchronizer circuits (see SN74120.pdf). I found it very useful to gate an oscillator on and off and not have to worry about partial or truncated pulses getting through to the output. The circuit ensured that complete pulses were sent to the output no matter when the gate was enabled or disabled. Unfortunately, no other vendor to my knowledge picked up the circuit and it was soon obsoleted.
Fortunately, the essential element of the circuit can be duplicated with simple logic gates. I am sure someone will find these circuits useful as I have.