why we use memory in controller?

[NorthGuy]

1) It doesn't. It has a program address bus. And it puts the current execution address on the program address bus. Then it reads the command code from the program data bus. It doesn't know how the code gets there. It could be a ROM module that puts it there, a RAM module, or anything else which the engineer deemed necessary.
2) same as 1, except it uses data bus (or some have a single bus).
3) see 1.

 

[Parth86]

I have uploaded circuit, I need some information.
If I am wrong somewhere please correct me
circuit contain mainly three part RAM, ROM, I/O port
memory - that means Rom where data and address is stored ?
reg file- that means Ram where the address of data is stored ?

If switch is connected to port P4 pin 1 (input)
and LED is connected to port P4 pin 2 (output)
code is burned in to the memory of controller (ROM)
Q1. when power is on, what is first step for microcontroller I mean first what do the microcontroller .
which circuit of microcontroller does work first ROM, Ram , I/o device

Processor take information from I/O devices
processor take information from RAM
processor take information from ROM

Q2. how does processor know that port Ppin 1 is high or low I mean how the ROM , RAM I/o device and processor work together ?
Q3. Is it correct?
fetching - control unit take information fro rom
decode - decoder take the information and send to processor
execute - processor do the operation. store result somewhere , I don't know where ?
Q4.why this question is very tough to understand for me?

 

[KeepItSimpleStupid]

Q1: Some things happen asynchonously or without the clock. Power-up resets certain states. That;s usually the job of the NOT RESET pin. Thats how ports get initialized to their default state. RAM generally powers up in a random state.

In modern processors there may be a short time to connect via JTAG or to download the firmware.

Nonetheless, a branch is started to a specific location depending on the architecture. It could be a branch to location 0. In a PDP-11 it's a branch to 173000 or 773000 octal.

The specific processor determines exactly what happens.

If you want to get really nuts, here https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0CCkQFjAA&url=https://www.nxp.com/documents/user_manual/UM10360.pdf&ei=5wc3U5LqFs6-sQTCw4DYCg&usg=AFQjCNE4UJrpOYQQCnRgxetOEDSvLaCiWw&sig2=4QEHEuN6iieY6QFiFVKxxA&bvm=bv.63808443,d.cWc is an 800+ page user manual for a processor.

Power down
In early processors, pulling the plug so to speak might have been the only option, but there was a need to use interrupts on power down as well. When there was an probable power failure, the process would branch to an ISR (Interrupt Service Routine) and "clean up" so to speak. Write stuff to disk etc. so an orderly shutdown would occur. Larger computers used the AC power line as sort of a Watch Dog Timer and for timekeeping.

maybe what you need is a much simpler processor: Here is the COSMAC1802 from 1977 https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=9&cad=rja&uact=8&ved=0CEoQFjAI&url=https://datasheets.chipdb.org/RCA/MPM-201B_CDP1802_Users_Manual_Nov77.pdf&ei=JQw3U-OdBsLIsASp-YKQBQ&usg=AFQjCNGyEVZLUkaqBJvZs6Bs4WfaNlUGTg&sig2=tmyxXzCgp-noQBSdHLLmlA&bvm=bv.63808443,d.cWc which I did program. Note, it has no gosub instruction.

Maybe we need to go back to one of the earliest microprocessors the Intel 4004 which migh be used in calculators. https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ved=0CC8QFjAB&url=https://www.intel.com/Assets/PDF/Manual/msc4.pdf&ei=NA03U62JEqPMsQT5oYD4Aw&usg=AFQjCNEtdeOqutCm4c064a77PYWsuE5tag&sig2=3I8k0DYA0KMzovNFtBmIIw&bvm=bv.63808443,d.cWc

The AMD2900 series https://en.wikipedia.org/wiki/AMD_Am2900 of chips came out in like 1975 and were the basis to "grow your own processor". These were essentially "components" of a full fledges CPU archetecture.

We can go back even further to 1965 and look at the PDP-8 **broken link removed** This was not IC based. The whole point, it should be simpler to understand, I also programmed this machine.

Id love to be able to post my lab notes, but I don't have time for it. It basically had instruction and data space implemented as RAM, a few registers, an ALU of sorts and a program counter all built from 7400 series IC's.

No real power on reset behavior. Not sure what buttons it had. I know I could slow the clock.

 

[Parth86]

I think I have to do more study but I have little doubt please correct

fetching - decoder take instruction from rom memory
decode- decoder decode instruction ans send to the ALU
execution-ALU do simple operation like ADD , mov, and result Save into Ram memory

program counter execute Instruction one by one

 

[KeepItSimpleStupid]

Fetch - get instruction somehow. The method isn't important, that's why we call it Fetch.
Decode - What kind of instruction is this?
Execute - Do whatever the instruction requires. It may not be one thing.

I think I know what your doing and it may be because of your style of learning, You can probably memorize easily, but have trouble with concepts.

Memory can be a combination of visual, verbal and kinesthetic. The latter item is like learning by repetition or learning how to ride a bike.

Verbal is by reading or speech. How well can you take directions from a stranger?

Visual is just that. Vision. My doc could visualize an entire page of a textbook in his mind. it's hard in a forum to do a visual presentation.

Unfortunately, what you have to learn here is concepts, not 1+1=2. Concepts might be better presented visually.

Every computer, controller implements the Fetch, decode and Execute in various ways.

One concept that is important in this study is the CISC and RISC architecture. CISC means Complicated Instruction Set Computing and RISC means Reduced Instruction Set Computing. In the latter, each instruction generally required one clock cycle to execute and the instructions are simple.

To give you an idea of a really CISC computer, lets look at the VAX architecture. You can find a character with a machine instruction. See: https://www.cs.auckland.ac.nz/references/macvax/op-codes/Instructions/locc.html

So, your definition falls out the window. With Fetch, Decode and Execute abstractly defined, it still is valid.