You're talking about the time constant - not the time delay.
A time delay assumes there is a delay before something is actioned. The delay would depend on how far up the charging curve the charge on the capacitor has to be before the delayed device is triggered. For example, if a CMOS gate is being used for the trigger threshold, then it may be anywhere between 30% and 70% of its final value, resulting in about a 4:1 variation in delay time
v=Vf*(1-e^(-t/R*C)), where v is the voltage across the cap at time t, and e is Napier's constant, e=2.71828......, which is the base for natural logarithms.
Solving for t, t=-R*C*ln(1-v/Vf), where ln is the natural log operator.
When v/Vf=0.5, t=0.693*R*C
In other words, it takes 0.693RC seconds for the capacitor to charge to half the supply voltage (0.5*Vf).
Using the first equation, when t=RC (one time constant), the cap will have charged to 0.632*Vf.
The time constant is the product of C and R. I had not seen a reference to 0.693 before and did not realise its significance until Ron's reply.
Ron H said:
....In other words, it takes 0.693RC seconds for the capacitor to charge to half the supply voltage (0.5*Vf).
Using the first equation, when t=RC (one time constant), the cap will have charged to 0.632*Vf