Ron H said:Jim brought up a good question: How do you want to determine the discharge rate? And why do you think it will impress the hell out of your instructor when you show him this marvel of electronics? :wink:
I gotta tell you, I'm beginning to wonder if you are taking a class in psychoelectronics. I think your assignment is to see how far you can drag some hapless design engineer (me) around by his ego. :roll:
When I ran the sim with zero volts on the input, the ramp output rose exponentially to 1.9V. I think the results of a sim will depend on the models you use, and actual hardware will behave somewhat differently.But, I noticed that the output continues to exist even when the input reverts to zero
Ron H said:When I ran the sim with zero volts on the input, the ramp output rose exponentially to 1.9V. I think the results of a sim will depend on the models you use, and actual hardware will behave somewhat differently.But, I noticed that the output continues to exist even when the input reverts to zero
So what do you actually want to do?
Ron H said:Do you want the cap do discharge linearly (constant current), or would exponential (resistor) be OK? If you want a constant current, we will probably have to add a negative supply.
I'm assuming that the input voltage is an independent variable. What does the input voltage do when the cap voltage gets to zero? Does it stay at zero? I believe you mentioned a one-shot ramp generator. It may be easier to simply divert the charging current to GND instead of clamping the input voltage to GND.
BTW, do you have a time limit here, or can you keep fooling with it 'til the cows come home?
Ron H said:The trouble with the dual slope integrator is that, IMHO, you dont have time to do it. It requires counters and logic (or something like a PIC) to implement it. And an op amp integrator is a MUCH better way to do it. See **broken link removed**.
Regarding your last post - If you clamp the input voltage to zero, what is going to cause that clamp to be released? Are you going to do it with a mechanical (pushbutton) switch, or does it release after a fixed period of time, or... :?:
I don't think you understand my question. Where does your input voltage come from? When the input voltage gets clamped, it doesn't go away, like the charge on the cap does when it gets discharged. The input voltage is still there - it is just "disconnected" from the input. If you release the input clamp as soon as the cap discharges, the cap will start to charge again. Then you have an oscillator, as we have discussed. If, on the other hand, you latch the input clamp, you will need some sort of external stimulus to reset the clamp.e-l-e-c-t-r-o said:Ron H said:The trouble with the dual slope integrator is that, IMHO, you dont have time to do it. It requires counters and logic (or something like a PIC) to implement it. And an op amp integrator is a MUCH better way to do it. See **broken link removed**.
Regarding your last post - If you clamp the input voltage to zero, what is going to cause that clamp to be released? Are you going to do it with a mechanical (pushbutton) switch, or does it release after a fixed period of time, or... :?:
As the graph indicates, the clamp-release occures after "change of condition between in/out voltage levels".
You can see that the clamp condition starts when the output (capacitor voltage) gets greater than input voltage.
The clampl of both in/out occurs until the point where the output becomes less than the input.
Of course, that operation requires the input voltage to be clamped much more drastically than the output 8)
Is that possible? :roll:
Ron H said:I don't think you understand my question. Where does your input voltage come from? When the input voltage gets clamped, it doesn't go away, like the charge on the cap does when it gets discharged. The input voltage is still there - it is just "disconnected" from the input. If you release the input clamp as soon as the cap discharges, the cap will start to charge again. Then you have an oscillator, as we have discussed. If, on the other hand, you latch the input clamp, you will need some sort of external stimulus to reset the clamp.e-l-e-c-t-r-o said:Ron H said:The trouble with the dual slope integrator is that, IMHO, you dont have time to do it. It requires counters and logic (or something like a PIC) to implement it. And an op amp integrator is a MUCH better way to do it. See **broken link removed**.
Regarding your last post - If you clamp the input voltage to zero, what is going to cause that clamp to be released? Are you going to do it with a mechanical (pushbutton) switch, or does it release after a fixed period of time, or... :?:
As the graph indicates, the clamp-release occures after "change of condition between in/out voltage levels".
You can see that the clamp condition starts when the output (capacitor voltage) gets greater than input voltage.
The clampl of both in/out occurs until the point where the output becomes less than the input.
Of course, that operation requires the input voltage to be clamped much more drastically than the output 8)
Is that possible? :roll:
I think the key point I'm trying to make is that the input voltage is (in my mind) an independent control voltage. If it goes to zero when you clamp it, how does it assume a non-zero value some finite length of time later?
Ron H said:That's too complicated. I'm still not really understanding you. I don't have time to figure out what you want and then design it.
Ron H said:I made one error in the schematic. It works as I drew it, but I'm posting a new schematic with the inverting input of U5 connected to C1 instead of ramp, which is the buffered output. It will be easier to describe the operation with this change.
I also realized that it would probably be better to connect the output of U3 to the PRESET input of A1, and tie the CLK input to GND. This should prevent the potential lockup condition which can occur, at least in the sim, and maybe in hardware. I solved it in the sim by setting .IC v(cap)=0. I didn't make this change on the new schematic.
I can't sim this now, because the file is in my computer at work, and I'm at home. I'll try to describe how it works.
You already know how the VCCS, the current mirror and the voltage follower work.
Q6 and R12, when Q6 is on (it is initially off), provide the current sink which will discharge C1 linearly. U3 is a comparator that senses when the ramp exceeds the control voltage. When this occurs, U3's output rises abruptly (guaranteed by the slight amount of positive feedback through R6), clocking a logic "1" (vcc on the D input) into A1 and causing A1Q to go high (vcc) and Q/ to go low (0V). This forces about a milliamp through D5 and D6, cutting off Q1, which in turn shuts off the current into C1 (this is equivalent to clamping the control voltage to zero, but is easier). At the same time, current ceases to flow through D3 and D4 (Q/ had been high and is now low), so Q6 turns on, discharging C1 with a current of about (9-0.7)/82k=100uA. C1 voltage slopes in a negative direction until U5 senses that it has gotten to GND (which is on the + input pin). When this happens, U5 output goes positive by 2 diode drops (approx +1.2V), clamping C1 to zero volts by diverting the discharge current, which was flowing through C1, through D1 and D2. With 1.2V on the U5 output, Q3 turns on, which turns off Q4. This applies vcc to the CLR input to A1, causing the outputs to switch states. This turns off the discharge current sink Q6 and simultaneously enables Q1 once again (by cutting off D5). If a non-zero control voltage is present, C1 will begin to charge again. If the control voltage has gone to zero (as you showed in a previous post), C1 will float, and may slowly charge due to U1 and U2 offset voltages and U4 input bias current (it can't discharge further, because U5 prevents it). Floating is not desirable, but it is one of the scenarios you proposed.
I hope this makes sense. I'm gonna be out of town for the rest of the week, starting around noon tomorrow.
Ron H said:I changed the connection from U3 output to A1 PRE, as discussed above. I ran the sim for two different input scenarios, as shown. If you need more, you'll have to figure out how to run the sim.
With zero control voltage, the ramp actually oscillates between ~+18mV and -18mV (this occurs during the time I predicted the "float". I was wrong.). The control loop tries to keep it at zero, but propagation delay around the control loop makes it oscillate. This could be minimized by using faster transistors (Q3 and Q4), faster op amps (U4 and U5), a faster comparator (U3), and a faster flip-flop (A1). Using a faster Q6 would be of little help, because it doesn't saturate (no storage time).
Various other schemes could be devised to speed up the loop, but I think it is impossible to totally eliminate the oscillation, due to the digital device (A1) in the loop.
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