Yes, any DC offset is corrected by the integrator C4 with the Gate R7 being the highest series R in the shunt across C4. The uC DAC sets the desired current , the 1 ohm senses it and the integrator FET driver provide the error correction to match the input from the DAC (DC or AC within integrator BW ) which attenuates any coil cable LC resonance, if that is a much higher f.
We do not know the LC parameters but the 1 ohm is power limited for current. e.g. << 0.25A for 1/4W or 5A for 5W. @ 150'C so the current sense R is normally derated by 50% for power to reduce temp rise by 50%. Likewise the FET drops from 12V voltage and dissipate >10X more heat than R14 so the DAC output voltage must be limited much less than 0.5V, I expect, unless the FET has a massive heatsink. SO the FET would be cooler if the drain was connected to 5V or even cooler from a 1Vdc supply.
e.g. if 0.25V was output from DAC then R14 dissipates 0.25W and the FET dissipates (12-0.25V )* 0.25A= 3 Watts. (more than 10 times R14.)
Is there PWM involved? That would make the FET cooler and provide an average current more efficiently and not heat up the FET as much. That is what I see.