voltage drop

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samina

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can anyone tell me why the voltage drop or loss occur at different logic gates
for example the input of an And gate was 3.3 v and output was 2.9, why it happened?
 
Ideally the output should be 5 V.But since you are drawing some current from its output,there is
some voltage drop in the internal resistance.The more current you draw,the less voltage you get
 
5V is not the ideal output from 3.3V logic.

The rest of the answer is correct; the output will always be some amount less than the power supply due to resistance and other losses.
 
A Cmos output goes up to the supply voltage when it drives Cmos inputs.
Old TTL outputs have base-emitter and resistor voltage drops at their output.
 
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