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Very Weird Problem in Verilog

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wuchy143

Member
HI All,

I've been able to make a music box partly with my code below. For some reason I cannot get the output to happen on output reg "AUD_L" without using the second always statement in my code. I shouldn't need to do that and I'm more than baffled by it. What am I missing?

`timescale 1ns / 1ps
module waveform_gen(AUD_L, reset_n, COUNT_VAL, CLK_50M, LED);
input [15:0] COUNT_VAL;
input reset_n;
input CLK_50M;
output reg AUD_L;
reg [15:0] counter, counter2;
output reg LED;



always @(posedge CLK_50M or negedge reset_n)begin
if(reset_n == 1'b0)begin
AUD_L <= 1'b0;
counter <= 16'd0;
end else begin
counter <= counter + 1;
case(counter)
COUNT_VAL: begin counter <= 16'd0; AUD_L <= ~AUD_L;end
default: AUD_L <= AUD_L;
endcase
end
end

always @(posedge AUD_L)
if(reset_n == 1'b0)begin
LED <= 1'b0;
counter2 <= 16'd0;
end else begin
counter2 <= counter2 + 1;
case(counter)
100: begin counter2 <= 16'd0; LED <= ~LED;end
default: LED <= LED;
endcase
end



endmodule
 
Just for clarification AUD_L is the monotone signal to a headphone jack on my Spartan 3an dev board which I have hooked in my headphones. It reads the switches on my dev board and can play 16 different notes.
 
Try this:

Code:
always @(posedge CLK_50M or negedge reset_n)begin
  if(reset_n == 1'b0)begin
    AUD_L <= 1'b0;
    counter <= 16'd0;
  end 
  else begin
    if(counter == COUNT_VAL)begin 
      counter <= 16'd0; 
      AUD_L <= ~AUD_L;
    end
    else begin  
      counter <= counter + 1;
      AUD_L <= AUD_L;
    end
  end
end
]

If this doesn't work, get busy with the simulator and find out why. If you're not using the simulator, you should learn to.
 
Last edited:
hmm. I see what you've done and that makes sense too. though when I run it on the hardware I don't get sounds out or any output for that matter. When I use the simulator it works fine for my code and yours. The signal which goes out to the headphone jack has the correct output frequency in the sim.
 
Maybe your .ufc file doesn't have the corret pins for the headphone jack??? Doube check it. Also you can check it against the schematics. This should be working. Can you verify the output with a scope or logic analyzer?

Also, don't forget you have "chip scope" at your disposal.
 
Last edited:
yes i'm able to verify my output with a scope. though I only get an output on the AUD_L pin when I use the second always statement. I take out that statement and it doesn't work.
 
sorry to waste your time. Looking my code over I didn't even put "reset_n" into my UCF. So I put it in and it works! and now I dont need to put in that second always statement which confused me. I guess not defining "reset_n" and leaving it open causes things to not work right....which I guess makes sense
 
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