What's important to remember about looking at signal quality on RS-232 is it not the best case p-p voltage that counts but the worst case... in which case all you show is +/- 3 to 4 V, which means loss of margin.
But the real threshold for ALL Rs-232 is the same as TTL which is ~1.3V ( 2x Vbe drops )
Imagine the start bit edge is when the clock synchronizes with a 16x clock then samples the 8/16th internal clock sample supposedly in the middle of the bit. Notice your rise time is horribly slow except the last bit (?) THis may be controlled by the 47pF caps being a little too big. or more likely to missing details in your copy of the design, lack of proper clean +/-6V..
Fix the supply rails.