CONFIG PLLDIV=5,CPUDIV=OSC1_PLL2,USBDIV=2,FOSC=HSPLL_HS,IESO=OFF
CONFIG VREGEN=ON,CCP2MX=ON,WDT=OFF,WDTPS=32768,PBADEN=OFF ,PWRT=OFF,MCLRE=ON
CONFIG LPT1OSC=OFF,BOR=ON,BORV=2,STVREN=ON,LVP=OFF,ICPRT= OFF,XINST=OFF,DEBUG=OFF
CONFIG WRTB=ON
PLLDIV=5 ' This sets the PLL Postscaler to divide the primary osc input by 5
providing 4MHz to the 96MHz PLL. The 96MHz PLL input must always be 4MHz
as shown in the data sheet.
CPUDIV=OSC1_PLL2 ' This sets the PLL Postscaler to divide the 96MHz PLL
output by 2 providing a 48MHz clock to the CPU.
USBDIV=2 ' This divides the 96MHz PLL output by 2 providing 48MHz to the USB core.
FOSC=HSPLL_HS ' This enables HSPLL for high-speed crystal/resonator.