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Two transistor forward SMPS with synchronous rectifiers...the only safe way to do it?

For a realistic offline 2 Transistor forward converter with synch rects, the attached is the only realistic "modus operandi" to do it.
Would you agree?
The synch rects get switched off before the primary fets turn ON. There is no chance of reversing output inductor current in light load, as there is a load current monitor which disables the synch rects in cases of light load current.
This is backed up by a comparator which looks at the COMP pin of the primary side controller. Whenever this goes low in voltage, indicating light load, then again the synch rects are turned OFF. Thus there is no chance that the synch rect logic could end up keeping the "freewheel" synch rect ON permanently during light load.
Do you know why there are no offtheshelf chipsets which incorporate this circuitry?

LTspice sim and pdf schem attached
 

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ChrisP58

Well-Known Member
Most Helpful Member
If there is one thing that I've leaned in my 40 plus years in electronics, there is never only one way to do anything. There isn't even a single best way.

And this is not just limited to electronics. It applies to just about everything in life.
 

ronsimpson

Well-Known Member
Most Helpful Member
It is not "Flyback" because; by now he would have come back and defended his schematic.
It is not "Flyback" because; by now he would have come back and argued ............. .
Sorry for getting off topic but you asked for it.
There are many very large ICs with pins to drive MOSFET-Diodes. Is that on topic?
 
Hi Ron,
Thankyou so much..that ISL6752 is fantastic. {EDIT/..But please see below post /EDIT}
It is the only Full bridge Driver IC I’ve ever seen which allows dead time setting long enough to always allow any current sense transformer to reset.

I would pick the schematic on page 5 and add logic chips so that I could use the complementary gate drive outputs to drive the lower fets directly instead of via the pulse transformer. But the high side FET drive is very impressive…..its always 50%, so no worries with varying gate drive voltage with varying duty cycle.

I am just reading it to check that the sych rect drive period can be well and truly timed so that there is a delay in between its on time and the ON time of the opposite primary phase ON time…..and whether the synch rects get disabled in light load.
 
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Actually, would you agree that the drive waveforms for the lower bridge fets and the synchronous fets on page 15 and 16 of the ISL6752 datasheet are mostly totally incorrect?....
Fig 19 is actually correct, but its on a “knife edge”, there being no delay between switching of the lower bridge fets and synch fets. But its “basically” correct, since each synch fet is on for its relevant bridge fet’s on-time, and also for the “freewheel” time.
Fig 20 and Fig 21 show each synchronous fet being ON when either left or right side lower bridge fets are on, and this is incorrect.

ISL6752 datasheet

Also, on pages 4 and 5, they have mis-connected the current sense transformer, for some reason referencing it to the Vdd rail.
 

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