• Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

STM32F4-Discovery PDR_ON

AtomSoft

Well-Known Member
Ok there is a PDR_ON pin which i can see is the Power Down Reset pin.... but how does one connect to it?

I tried following the schematic on the STM32F4-Discovery board but it tells me R27 isnt fitted.. i assume that means its not populated and it says nothing on R28. Both resistors touch the PDR_ON pin. So im not sure what to follow?

Should i do whats on the board and FIT a 0 ohm or straight connect VDD.... ? or listen to schematic and tie to GND?

Im kind of lost... Attached are pictures of the schematic portion from the Discovery Datasheet and the actual board image where R27 is in place but not R28...

Perhaps its a silk screen error?
 

AtomSoft

Well-Known Member
Ok in another datasheet i notice:
Power-on reset (POR)/power-down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting from
to 1.8 V.
The device remains in Reset mode when VDD/VDDA is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit. For more details concerning the
power on/power-down reset threshold, refer to the electrical characteristics of the datasheet.
So i think i should tie to VDD with either a 0 ohm or straight

UPDATE: It is tied to VDD on my board... just used a DMM to figure it out. So i guess R27 is fitted and R28 isnt fitted. Perhaps a schematic note error.
 
Last edited:

AtomSoft

Well-Known Member
In another datasheet i found this info:

All packages, except for the LQFP64 and LQFP100, have an internal reset controlled
through the PDR_ON signal.
Regulator ON
● Regulator ON/internal reset ON
The regulator ON/internal reset ON mode is always enabled on LQFP64 and LQFP100
package.
On LQFP144 package, this mode is activated by setting PDR_ON to VDD.
On UFBGA176 package, the internal regulator must be activated by connecting
BYPASS_REG to VSS, and PDR_ON to VDD.
On LQFP176 packages, the internal reset must be activated by connecting PDR_ON to
VDD.
The regulator ON with internal reset OFF mode is not available on LQFP64 and
LQFP100 packages.
On LQFP144, and LQFP176 packages, the internal reset is controlled by applying an
inverted reset signal to PDR_ON pin.
On UFBGA176 package, the internal regulator must be activated by connecting
BYPASS_REG to VSS.
On LQFP176 packages, the internal reset must be activated by applying an inverted
reset signal to PDR_ON pin.
The NRST pin should be controlled by an external reset controller to keep the device
under reset when VDD is below 1.8 V (see Figure 7).
Crazy how all of this is separated into different parts... But I will conclude that it has to be:

TIED to VDD

Even tho it says its not used on LQFP100 and LQFP64 but JUST IN CASE! since it is available i recommend to tie it to VDD since that's what's need to be done for the other packages and what is done on the actual PCB.

I hope this is useful to others out there.
 

AtomSoft

Well-Known Member
Take a look:

In the schematics UM1472, page 31, figure 11, you will find a note fro R27 and R28 based on the board revision. Our earlier STM32F4Discovery boards have R27 fitted and R28 not fitted.

UM1472 Discovery Board User Manual is found here:
http://www.electro-tech-online.com/custompdfs/2012/03/DM00039084.pdf

The reason for this change is described in our errata which is found here:
http://www.electro-tech-online.com/custompdfs/2012/03/DM00037591.pdf

The change is necessary based on the revision letter of the STM32F4 silicion (A,Z). Section 2.1.6 states:

+++
2.1.6: PDR_ON pin not available on LQFP100 package for revision Z devices

Description

On revision-Z devices, the PDR_ON pin (pin 99) available on LQFP100 package is replaced
by VSS. As a consequence, the POR/PDR feature is always enabled.

Workaround
● Applications using on revision A devices with PDR_ON pin connected to VDD (POR/PDR feature enabled) Connect the former PDR_ON pin to VSS on revision Z devices.
● Applications using revision A devices with PDR_ON pin connected to VSS (POR/PDR feature disabled)

No modification is required when migrating to revision Z devices. However, it is no longer possible to supply the product from a 1.7 V VDD on LQFP100 package since VDD minimum value is 1.8 V when the POR/PDR feature is enabled.

+++

It appears you have a first revision discovery board with a revision A device (first production silicon). For any future designs, please prepare for revision Z devices and adjust PDR_ON pin accordingly.

Best Regards,
MCU Technical Support
 

Latest threads

EE World Online Articles

Loading

 
Top