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SRAM MODULE how it works ?

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Lucyfer

New Member
Hello guys! im pretty new on electronics and now i have to simulate a sram memory in the spice3 program.... the prob is that in the picture i found out i cant find the gate/source/etc points
would you plz help me ?
thanks yall
 

Sceadwian

Banned
I find it highly unlikely you'll be able to find a spice model for an SRAM module, real spice models for complex devices like that are closely held at the chip maker and not released to the public, exactly why are you trying to simulate one?
 
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Lucyfer

New Member
well i just started researching at my university and the person who orientates me 1st told me to read sumthing bout transistor...
now i know about nmos pmos, etc..
ok... now he said... to research abut the results of the ionic radiation over a IC youll 1st need to simulate a basic sram (6 transistors) in the hspice or in the spice3...
plus he said: feel free to discover how...
ive googled it and found a simple sram ( 6 transistors) at the wikipedia.org ( im new here sorry if ive done something wrong with this site posting)
i have a picture of it ... and here it is File:SRAM Cell (6 Transistors).svg - Wikipedia, the free encyclopedia

i just need to know what exactly goed in and what goes out... its a very simple question i am sure... but what is BL, Vdd, WL ?
i was used to give other names for the transistor legs... so where do i put my source... and where is the output ? =P
ty
 

Lucyfer

New Member
just addicting some info..
i am using the caipirinha grafer 0.5 ( made in Universidade Federal do Rio Grande do Sul, Brazil)... plus the spice3 simulator for windows....
by now im programing basic circuits like trying single transistors, making inversors and from now on.. im simulating sram modules.. why ? cuz we wanna know the effect of the radiation on it... and while i cant use real radiantion we have to simulate it...
how do i make it ?
when it was a inversor i used to do simething like this

Inversor

.include f:\spice\ams35ps.lib
Va VDD 0 5

Vb IN 0 pulse(0, 5, .3ns, .5ns, .5ns, 10ns, 20ns)
M1 VDD IN OUT VDD MODP L=0.6u W=4.2u
M2 0 IN OUT 0 MODN L=0.6u W=1.4u
Ca OUT 0 10ff

.TRAN 1p 40n
.print TRAN V(IN) V(OUT)
.probe

.END

to create a *.cir file that in the prompt could be tranformed into a *.out file
in this case im using 35nm technology (generated by berkeley university system)....
after transforming the .cir into a .out with the command : "spice3 -b file.cir > file.out" all u have to do is to run the grafer that will show the Vin / Vout behavior.

thanks by now
best regards
 
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Sceadwian

Banned
I think what you're trying to do is WAY over the head of any user on this board. You're talking about simulating chip level cmos circuits. That's not exactly common place.
 

FusionITR

Member
Ok, I'm a little confused at what youre right to do.

You want to sim an SRAM cell? You have the schematic, just two back to back inverters and pass gates for bit and bitb. Nothing complicated. Are you trying to see the transient response of changing the value of the SRAM cell? Just drive bit and bitb (BL and BLbar) in your schematic and toggle the WL.
 

Lucyfer

New Member
im trying to make this sram cell work in my spice3... now i wanna know witch leg os the transistor are respectively connected with my source.. my gate and my drain... the prob is that ive found that schematics on the internet and i dunno exaclty which legs of each transistor are my G, S & my D.
after this ill problably know what to do....

actually all i got to do for now is to change de Vin value or the wave type
and analyse which is de Dif betwen the Vin/Vout... after this i cant post what i was told to do =]

now sceadwian.. about this forum... ure not used with questions like these? thats what u mean ?
if was that sorry.. i asked here cuz i dont know ne where else to ask for this kind of help =]

thats by now
best regards
 

Sceadwian

Banned
No, simulating SRAM cells in spice doesn't come up much on the forums here. I'm not sure why you're having trouble translating the schematic, the Gate is obvious, the drain is the conenction on the top or left, and the source is the connection on the bottom or the right. The one's with the little circles at their gates are pmos fets, at least that's the way I read it. I might have the horizontal fets wrong but if it doesn't work swap them.
 
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Lucyfer

New Member
ok guys this topic got its answers!
nw that i have finally done the SIM...
here is the program schematics for spice3 if ne 1 ever searches for it... elctro-tech-online will be the only place that will have it..

spice3 code for SRAM module (6 transistors), based on berkeley transistor model for 35nm structure:


MODULO_SRAM


.include c:\gabriel\spice\ams35ps.lib

Va VDD 0 5

Vb IN 0 pulse(0, 5, .3ns, .5ns, 10ns 20ns)
M1 VDD IN OUT VDD MODP L= 0.6u W= 4.2u
M2 0 IN OUT 0 MODN L= 0.6u W= 1.4u
M3 VDD OUT IN VDD MODP L= 0.6u w= 4.2u
M4 0 OUT IN 0 MODN L= 0.6u W= 1.4u
Ca OUT 0 10ff

.TRAN 1p 40n
.print TRAN V(IN) V(OUT)
.probe

.END



also i would like to thanks sceadwain and fusionITR cuz without their answers i wouldnt have took the point of it =]
see ya
 

Sceadwian

Banned
Glad you got an solution Lucyfer.
 

FusionITR

Member
ok guys this topic got its answers!
nw that i have finally done the SIM...
here is the program schematics for spice3 if ne 1 ever searches for it... elctro-tech-online will be the only place that will have it..

spice3 code for SRAM module (6 transistors), based on berkeley transistor model for 35nm structure:


MODULO_SRAM


.include c:\gabriel\spice\ams35ps.lib

Va VDD 0 5

Vb IN 0 pulse(0, 5, .3ns, .5ns, 10ns 20ns)
M1 VDD IN OUT VDD MODP L= 0.6u W= 4.2u
M2 0 IN OUT 0 MODN L= 0.6u W= 1.4u
M3 VDD OUT IN VDD MODP L= 0.6u w= 4.2u
M4 0 OUT IN 0 MODN L= 0.6u W= 1.4u
Ca OUT 0 10ff

.TRAN 1p 40n
.print TRAN V(IN) V(OUT)
.probe

.END



also i would like to thanks sceadwain and fusionITR cuz without their answers i wouldnt have took the point of it =]
see ya
No prob, glad to help :)
 
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