I didn't mean that the voltage across the load that would be 4.3V, but between the Gate and the Source terminals of the FET which is OK if it is a logic level FET. This will also contribute to the crappy rise time in a real life circuit. eg as per your SIM: So when the FET is ON then there would be 19.8V on the source and 24.1V at the Gate meaning there is only 4.3V left to turn the FET on.
Probably not. More to illustrate the need for a common emitter config as opposed to the emitter follower posted by Clipo.