shorter machine cycle, increase number of MC's per instruction, performance boost

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PG1995

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Hi

Please have a look on the attachment and kindly help me with the queries. Thanks a lot.

Regards
PG
 
Because the number of clocks per machine cycle was decreased from 12 to 1. A typical instruction cycle requires a fetch, decode, execute, write, etc. Type "Instruction Pipeline" into Wikipedia.
 
Q2: You have a point in theory, except you need to consider the actual ratios involved. Clocks to machine cycles went from 12 :1 to 1:1 (i.e., a 12-fold improvement). None of the machine cycles to operation ratios increased that much. Thus, there is improvement in speed.

John
 
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