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Shift Register project...

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jrz126

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Here's another question about my shift register project.

I'm using 8 shift registers, wired in series. shift 1 bit in, it will travel through all 64 bits before it reaches the end.

What I'm trying to do is, only have 4 to 8 bits set to '1'. and have the input to the SR's connected to the output, creating a loop. (once the bit reaches the end, it will be put back into the input).

I've gotten it to work by running the clock so that only 4 bits are 1's, then connecting the SR input to the SR output. This took some time to do, and required switch wires and stuff. Is there an easy way to do this so that every time I turn it on only 4 bits are 1's and it will loop in a circle?
I'd prefer to do it without a microcontroller.

(Sorry for the poor discription, I have class in about 2 minutes :( )


Here's a pic of part of the circuit.
 
If all these 1's need to be contiguous, connect an octal tri-stateable buffer (hc240 or 241, with appropriate input levels) to the I/O pins on one of the hc299's, then simultaneously:

1. Enable the buffer,
2. Disable only the outputs of the chosen hc299 (high impedance state),
3. Put the chosen hc299 in load mode,
4. Clear the remaining hc299's.
5. After 1 or more clock cycles, simultaneously disable the buffer, enable the chosen hc299, remove the clear on the others, and return to shift right mode.

This will take one control signal, and probably its complement, and it needs to be clock-synchronous.
 
Wouldnt the pullup's cause the bits to always be 1's?
 
FRIED said:
Could use pullups instead of the buffer
That's true. I was thinking that the buffer would allow the pattern to be changed by a microcontroller, but that may not be necessary.
Jeff, the pullups would need to be relatively light, like 10k. They would only provide logic 1's when the shift register is in high-Z mode.
 
I was thinking more like 1K to pull up with ULN2803 load. The outputs will pull this load down ok. All the remaining I/O are effectively pulled down by the ULN2803's so loading all of the registers at once will load the desired pattern. Since S2 should be high (shift R) this would involve taking S1 high for a clock.
 
FRIED said:
I was thinking more like 1K to pull up with ULN2803 load. The outputs will pull this load down ok. All the remaining I/O are effectively pulled down by the ULN2803's so loading all of the registers at once will load the desired pattern. Since S2 should be high (shift R) this would involve taking S1 high for a clock.
I forgot about the ULN2803's. :oops: I agree that 1k is about as high as you'd want to go for a decent logic 1 in Hi-Z mode, and just about as low as you'd want to go and still get a guaranteed logic 0 out of the SR (it has bus driver outputs, which is a plus). I think I like the tri-state buffer better. :)
 
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