Reviewer Wanted

Hi,

I designed a project in a software simulator (LogicCircuit). It's a very simple 'computer' (limited to six operations).

I'm hoping that someone will be interested in looking at the design. I'd really like guidance on improvements and corrections. I didn't design this based on any standard design/architecture and my purpose in creating it was to demonstrate some simple principles of electronics.

I want to improve the design but not necessarily add anything to it.

Thanks!

-- Details --

I've attached the LogicCircuit project and the program can be downloaded here.

I wanted to build the RAM from scratch but I used a ROM component for commands and a sensor to cycle through the bytes.

There are six commands:

Pass (no operation)
LoadX #v (with 4-bit value v)
LoadY #v (with 4-bit value v)
Mul (Multiply X and Y, result in A)
Add (Add X and Y, result in A)
Store v (A to 2-bit address v)

The connected ROM has this list of instructions:

You didn't show anything to review.

Should I upload the project file and then add a link to the software that you need to view it? This is new to me, so I'm not sure how best to proceed.

Okay, I edited the original post, attached the project file and added a link to the software. I also listed out the ROM bytes and the instructions. Please let me know if I need to provide more information. I think most of the circuits are fairly straight-forward and I tried to keep the project simple.

That is really complicated to be reviewed. One thing that strikes me is that you are using a thing called splitter to combine outputs together, how does that work?
Have you tested the design?

Also, why are you drawing it in schematic instead of writing code like verilog? Things are much easier to test when you can easily split to small units and write tests for each one.

Thanks for your reply. Do you mean the built-in splitter in LogicCircuit? Those are simply a way to minimize visual clutter by letting the user draw with fewer wires. It's not supposed to represent a real-world component.

I'm not sure what you mean, in regards to building small units. LogicCircuit lets you break things down into very small units, which is how that whole project was built. The 4-bit adder can be broken down into half-adders, which only consist of a XOR and AND gate. Likewise, the 'registers' can be broken down into single-bit memory circuits of only 4 NAND gates. I would suggest the most complex thing is the 4-bit multiplyer, which uses 16 AND gates and several half/full-adders.

The only thing I've tested outside of LogicCircuit is the memory circuit, which I physically built. As far as I know, LogicCircuit simulates things pretty accurately and the physical memory I built behaved exactly as demonstrated by the program. I don't know Verilog or VHDL but I'm going to try to learn one of those, if I have time. I would aim for VHDL because my favourite FPGA computer was written in VHDL.

logicrace said:

Thanks for your reply. Do you mean the built-in splitter in LogicCircuit? Those are simply a way to minimize visual clutter by letting the user draw with fewer wires. It's not supposed to represent a real-world component.

Click to expand...

A splitter for splitting, I don't have a problem with that. A splitter for joining outputs together, I have no clue what the outcome will be. Does it work like OR, or like AND, or something else? And sorry, don't have the time to go through the documentation if that is even a valid connection.

I'm not sure what you mean, in regards to building small units. LogicCircuit lets you break things down into very small units, which is how that whole project was built. The 4-bit adder can be broken down into half-adders, which only consist of a XOR and AND gate. Likewise, the 'registers' can be broken down into single-bit memory circuits of only 4 NAND gates. I would suggest the most complex thing is the 4-bit multiplyer, which uses 16 AND gates and several half/full-adders.

Click to expand...

What I meant was, how easy is it to take that block and put it to test, i.e. set some sets of inputs and clock and watch what comes out and check if it is correct. Testing of standalone units one by one is really what gets logic design going. If you can do it simply and painlessly, then go for it. If you can't, start looking for another tool to express the logic behind your design.

The only thing I've tested outside of LogicCircuit is the memory circuit, which I physically built. As far as I know, LogicCircuit simulates things pretty accurately and the physical memory I built behaved exactly as demonstrated by the program. I don't know Verilog or VHDL but I'm going to try to learn one of those, if I have time. I would aim for VHDL because my favourite FPGA computer was written in VHDL.

Click to expand...

Two things, the fact that what you draw behaves the same way as a physical thing is nice to have aka mandatory, but it doesn't really help you find what problems you have and where they are.
Second, I would still suggest verilog (my personal opinion) as it is a bit less verbose than vhdl, so I like more working with it more, but really both can do the job just as well.

The key part in logic design is testing. As you have it now, basically all you can do with the design is run that code and see what comes up. In HDL languages like verilog or vhdl you can make code that runs the simulation and checks the expected results at the same time. That way when you fiddle with the inner workings, trying to get more speed or or lower latency or whatever, you can simply run that test and be sure that you (probably) didn't screw anything up with the new changes.
But what is more important, it lets you check all the inner modules like ram and multiplexer and counter without copy pasting them out of the circuit - once you write a test for each module, you can allways be sure that what you have is correct.

So back to your original question, how is anyone to review what you have done? The complete circuit is quite complex and convoluted, so one would like to divide it into modules to check. As I remember, each module explodes into a bunch of interconnected gates, which still is very confusing. Which brings me to another nice thing about HDL languages, not only is usually the function of the circuit more or less apparent, you can have comments at each line to explain what is going on, which most of the time is hard to explain in schematics.

kubeek said:

A splitter for splitting, I don't have a problem with that. A splitter for joining outputs together, I have no clue what the outcome will be. Does it work like OR, or like AND, or something else? And sorry, don't have the time to go through the documentation if that is even a valid connection.

Click to expand...

It's valid. They're only combined visually. For example, if I have four wires - A, B, C and D - and I use the 'splitter' to combine them into one (4-bit) line, that one line still represents the four ABCD wires. They will be treated logically as four, separate wires but I only need to draw one line to connect them to something else, e.g. a 4-bit input. That input would really be four pins on a physical IC. Hopefully, that makes sense.

Of course, the problem with that is that the program doesn't always make it clear what order they will be in.

What I meant was, how easy is it to take that block and put it to test, i.e. set some sets of inputs and clock and watch what comes out and check if it is correct. Testing of standalone units one by one is really what gets logic design going. If you can do it simply and painlessly, then go for it. If you can't, start looking for another tool to express the logic behind your design.

Two things, the fact that what you draw behaves the same way as a physical thing is nice to have aka mandatory, but it doesn't really help you find what problems you have and where they are.

Second, I would still suggest verilog (my personal opinion) as it is a bit less verbose than vhdl, so I like more working with it more, but really both can do the job just as well.

The key part in logic design is testing. As you have it now, basically all you can do with the design is run that code and see what comes up. In HDL languages like verilog or vhdl you can make code that runs the simulation and checks the expected results at the same time. That way when you fiddle with the inner workings, trying to get more speed or or lower latency or whatever, you can simply run that test and be sure that you (probably) didn't screw anything up with the new changes.

But what is more important, it lets you check all the inner modules like ram and multiplexer and counter without copy pasting them out of the circuit - once you write a test for each module, you can allways be sure that what you have is correct.

Click to expand...

Ah, good points. When I put it together, I was mostly interested in the physical simulation. Now that I have a design, maybe testing would be easier with what you suggest. I had to copy-and-paste circuits to test them, which wasn't a big deal when just testing that one part but it's hardly ideal.

So back to your original question, how is anyone to review what you have done? The complete circuit is quite complex and convoluted, so one would like to divide it into modules to check. As I remember, each module explodes into a bunch of interconnected gates, which still is very confusing. Which brings me to another nice thing about HDL languages, not only is usually the function of the circuit more or less apparent, you can have comments at each line to explain what is going on, which most of the time is hard to explain in schematics.

Click to expand...

Again, this is new for me. I didn't know what to expect or exactly how/what to ask. I was hoping someone could look at it and tell me if anything in the design was crazy or 'wrong'. Maybe someone could look at it and tell me how to improve it. I'm trying to get feedback from people who know this stuff better than I do.

I do know that reliability is not perfect, which I am sure is due to timing. Sometimes, a wrong number will appear in the selected RAM byte or (I think) the A register. I tried to do everything in single cycles but I didn't know how to time things to trigger the write-state when everything was ready and then go read-only immediately after. But maybe this is something that would be better to test as you describe - with an HDL.

That is an area where I thought someone might be able to provide insight or assistance. Looking at the register circuit, they might be able to tell me a simple way of making the write-enable latch flip intermittently when the data lines are populated.

The previous design for this has switches where the "command decoder" is. Everything works fine, when it's the user manually punching in numbers and operations using switches and buttons.

I'm also not sure what you think is so convoluted with the design, so maybe you can elaborate on that?

I've uploaded a new version (Comp7), where I've cleaned up and added comments to help explain things.