Resetting a Modulo 5 Down Counter

Hey I want to design a mod 5 down counter with a negative edge triggered jk bistables

All the examples I have seen have shown an up counter with the reset applied when the max number (and its equiv binary value) is acheived - then the count returns to 0.

In a down counter, Im not sure how to reset so that when it gets to value 0like so 5,4,3,2,1,0 - it resets back to 5,4,3,2,1,0 etc

I guess what i trying to say is how do i apply a reset to my 3 negative edge triggered j-k flip flops so that it goes from 5 down to 0 and then back to 5?

Its not homework but i think it will come up in my exam tmoro!

Can anyone help?

It's not that much different for a ripple down counter. You're going to use a 3-input NAND gate on the three Q outputs. When all three outputs go HIGH, the count has rolled from zero to 111 and the output of the NAND will go LOW. You tie the output of the NAND gate to the PRESET input of the least-significant and most-significant F/Fs and the CLEAR input of the middle F/F. This will force the count to 101 (decimal 5) when it tries to "undercount" to 111.

You're lucky it's a ripple counter. Modifying the count of a synchronous counter and keeping it synchronous is a bit more complicated.

By the way, there are six states in your count sequence making it a modulo-6 counter, not a modulo-5 counter. It's the number of states in the count, not the maximum count, that determines the mod/modulo/divide-by number. That would be a good test question, too.

Dean

Dean Huster said:

It's not that much different for a ripple down counter. You're going to use a 3-input NAND gate on the three Q outputs. When all three outputs go HIGH, the count has rolled from zero to 111 and the output of the NAND will go LOW. You tie the output of the NAND gate to the PRESET input of the least-significant and most-significant F/Fs and the CLEAR input of the middle F/F. This will force the count to 101 (decimal 5) when it tries to "undercount" to 111.

Dean

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Thanks a lot, I understand so much clearer than the textbooks I bought. One thing, im pretty sure about but should check, in count down I have to take the clock signal for following stages from Qinverse? So each clock signal should be fed from the Q inverse of the previous FF, but I still feed the 3 Q outputs (not inverse) to the NAND gate for my reset condition.