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# 'Resetting 24C02 I2C EEPROM' - confused

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#### p55xp

##### Member
Hello every one,
I have designed a mains power control system for home use around an AT89C51; it's working without any problem as long as mains power contiues. In case of a power failure 'last condition' never returns - as there is no
non-volatile memory.

So I decided to use one AT24C02 to memorize the 'last condition'. With every switching manipulation AT24C02 is written to. After a power failure when it restores again the AT24C02 is read and 'last condition' is restored too acordingly.

Now the problem is: as I go through the datasheets of all such I2C serial memories there is a memory reset in that of AT24C02 which is not present in others. All 24C02 s' are pin to pin replaceable, and as I have decided to use it for a relatively slow SCL (100 KHz), any 24C02 can be substituted. Is memory reset an utter requirement in bus master's firmware? If so please help me with its routine. Flowchart will do.

Thanks.

#### rushi53

##### Member
Now the problem is: as I go through the datasheets of all such I2C serial memories there is a memory reset in that of AT24C02 which is not present in others. All 24C02 s' are pin to pin replaceable, and as I have decided to use it for a relatively slow SCL (100 KHz), any 24C02 can be substituted. Is memory reset an utter requirement in bus master's firmware? If so please help me with its routine. Flowchart will do.

I have used AT24c02 many times. In projects like data logger, voting machine.
But I am hearing this concept (memory reset) for the first.

But when I use 24c02 in any project, first I erase all memory. This is done ONLY ONCE.
and then I install this IC in project and do read / write operations.

You can follow the same thing.

Please let me know if you need any more help

#### p55xp

##### Member
I have used AT24c02 many times. In projects like data logger, voting machine.
But I am hearing this concept (memory reset) for the first.

I attached 2 Datasheet; highlighted at page 4 of one (AT24Cxx) and page 6 of the other (AT24C02B). It may help you farther to view my problem.

#### Attachments

• I2C_memory.zip
536.5 KB · Views: 1,425

#### Pommie

##### Well-Known Member
This problem happens with any I²C device and is caused by the processor being reset whilst in the middle of a transfer. Normally, both devices get reset on power down and so the problem doesn't arise. During development you have the situation where only the processor is reset and the device is left waiting for the transfer to complete. Just follow the sequence in the data sheet to reset the bus.

Mike.

#### sa11

##### New Member
I attached 2 Datasheet; highlighted at page 4 of one (AT24Cxx) and page 6 of the other (AT24C02B). It may help you farther to view my problem.

This is not a memory reset. This is communication reset which can be used to get the 24c02 in sync if 89C51 and 24C02 get out of sync (that could happen any of the chips getting reset while the other one doesn't or bad I2c implementation)

#### p55xp

##### Member
Thanks Mike, for your interest in solving my problem

Should I check SDA for high in every SCL high upto 9 times and if SDA fails to be high in any SCL high then go back for a new cycle of 9 SCL ......so long as 9 times SDA become high in each SCL, and then creat a start condition?
Or,
Should I appply 9 SCL keeping SDA high and check SDA at the end for a high, and if SDA fails to be high then go back and apply 9 SCL ...... then creat a start condition when SDA is high?
Tell me explicitly which flowchart should I follow? because two of my attached datasheet directs different course of flowchart, may be I misunderstood the datasheet.

During development you have the situation where only the processor is reset and the device is left waiting for the transfer to complete. Just follow the sequence in the data sheet to reset the bus.

I decided to include one 'memory reset' routine at the beginning of my firmware, may be an overkill but it is safe I think.

Please help me to write a firmware so that any 24C02 can be substituted, or replaced without any hesitation.

Thanks.

Last edited:

#### Pommie

##### Well-Known Member
I just checked the way I have done this is the past. At reset, if I release the data line and it is still low then I send clock pulses until the data line is high.

Mike.

This is code for a pic but you can see how it's done,
Code:
void I2cInit(){
I2cDataTris=1;              //Make data input
I2cClockTris=1;             //and clock
while(!I2cData){            //if something holding line low
I2cClock=0;             //then pulse clock line
I2cClockTris=0;
I2cClockTris=1;
}
sspstat=1<<SMP;
sspcon=0x28;
pir1.SSPIF=0;
pir2.BCLIF=0;
}

#### p55xp

##### Member
Thanks Mike for your sincere approach.
I understand :
I just checked the way I have done this is the past. At reset, if I release the data line and it is still low then I send clock pulses until the data line is high.

I must try this way.

But I do not understand what you write as code: I understand only asembly language, that also for 8031/32/51/52 processors. I can realise PIC asembly language without any problem, but I don't know 'C'.

#### p55xp

##### Member
Really sorry for a long pause!

It is assumed that an AT89C51 is running at 12Mhz and SCL is 100 Khz,
please check whether the following code is correct?
Please correct the code if necessary.

I2CRESET: setb SCL
setb SDA
acall DELAY ; a DELAY for 5 uS inserted
clr SDA ;Start condition
acall DELAY
clr SCL
nop
setb SDA ;SDA raised
mov r5,#9
acall DELAY
NINE: setb SCL ;9 (NINE) clocks applied
acall DELAY
clr SCL
nop
nop
nop
djnz r5,NINE
setb SCL
acall DELAY
clr SDA ;Start condition
acall DELAY
clr SCL
acall DELAY
setb SCL
acall DELAY
setb SDA ;Stop condition
clr SDA
acall DELAY
clr SCL
acall DELAY
setb SCL
acall DELAY
setb SDA

DELAY: nop ;5uS DELAY 2uS for call and ret each and 1uS for nop
ret

#### Pommie

##### Well-Known Member
That looks correct but you don't need the last part,
Code:
I2CRESET:
setb	SCL
setb	SDA
acall	DELAY	; a DELAY for 5 uS inserted
clr	SDA	;Start condition
acall	DELAY
clr	SCL
nop
setb	SDA	;SDA raised
mov	r5,#9
acall	DELAY
NINE:	setb	SCL	;9 (NINE) clocks applied
acall	DELAY
clr	SCL
nop
nop
nop
djnz	r5,NINE
setb	SCL
acall	DELAY
clr	SDA	;Start condition
acall	DELAY
clr	SCL
acall	DELAY
setb	SCL
acall	DELAY
setb	SDA	;Stop condition
[COLOR="Red"]clr	SDA	;not needed
acall	DELAY
clr	SCL
acall	DELAY
setb	SCL
acall	DELAY
setb	SDA[/COLOR]

Edit, to make your code keep its formatting, like above, type
Code:
 before it and
after it.

Mike.

Last edited:

#### p55xp

##### Member
Thanks Mike,
you studied the Code so keenly that you pointed out unnecessary parts in red.
Code:
[COLOR="Red"]clr	SDA	;not needed
acall	DELAY
clr	SCL
acall	DELAY
setb	SCL
acall	DELAY
setb	SDA [/COLOR]
I do not have this part in my code, parhaps for some typing mistake I re-typed last 7 lines same as its preceding 7 lines before putting ;comments in it.

Thanks again,
Edit, to make your code keep its formatting, like above, type
Code:
before it and
after it.

Mike.
I don't Know this, and now you realise that I learnt this too from you.
Keep guiding

#### OmarElsherif

##### New Member
I2C Common Problems:

Pullup resistors (on Clock and Data pins).

Operation sequence (Write and Read Sequence):
- Write: Start - Device Address (write, LSb = '0') - Data Address - Data - Stop
- Read: Start - Device Address (write, LSb = '0') - Data Address - Start (Restart in Microchip PIC microcontrollers) - Device Address (read, LSb = '1') - Read - Acknowledge - Read - Negative Acknowledge - Stop. (Acknowledge if there are more Reads, Negative Acknowledge before stop).

Address size (Bytes): What i called (Data Address), could be byte or more.

After Write delay: You have to wait a small time after write operations (after stop, not during write). This delay will be needed in fast microcontrollers, if you don't delay you will read wrong data.

Read Initialization Flag (REN): This is in PIC, you have to initialize read operation and wait for BF (Buffer Full) or SSPIF (Interrupt Flag), and then read buffer register (SSPBUF in PIC microcontrollers).

Acknowledge: Don't forget to acknowledge during read operations, acknowledge only if you are going to read another byte, and negative acknowledge after the last read, right before stop. Negative acknowledge is done by inverting acknowledge polarity.

Acknowledge polarity: Acknowledge has negative polarity, while negative acknowledge has positive polarity.

Read bit: It's the LSb (least significant bit) of the (Device Address) byte, it should be '0' for write, and '1' for read

Write Protect pin (EEPROM): Connect this pin to VCC, or GND, or leave it floating, get this information from datasheet, for 24 EEPROM series, you can leave it floating.

Frequency: Ensure that the frequency you are working on is supported by the device you are trying to access.

Software Reset (I don't know when to use it, but i found it in AT24C02B datasheet): Start - Write (0xFF) - Start - STOP.

Last edited:
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