void Init_RFM70()
{
int8 Temp;
SwitchToBank(0); // Not needed, Bank should be 0 after reset
SPI_Write_Reg(CONFIG, 0b00001110); // Enable CRC - 2 bytes CRC - POWER UP - PTX
SPI_Write_Reg(EN_AA, 0b00000000); // Disable Auto Acknowledge
SPI_Write_Reg(EN_RXADDR, 0b00000001); // Enable data pipe 0
SPI_Write_Reg(SETUP_AW, 0b00000011); // 5 bytes address
SPI_Write_Reg(SETUP_RETR, 0b00000000); // Re-Transmit disabled
SPI_Write_Reg(RF_CH, 23); // Set the frequency channel to 23
Temp = SPI_Read_Reg(RF_SETUP); // Read existing values in register
Temp = Temp & 0b11110111; // Air Data Rate 1Mbps
SPI_Write_Reg(RF_SETUP, Temp); // Write value to register
SPI_Write_Cmd(ACTIVATE, 0x73); // Activate registers: R_RX_PL_WID - W_ACK_PAYLOAD - W_TX_PAYLOAD_NOACK
SwitchToBank(1);
// Write predefined value 0x404B01E2 to register 0x00
CSN = 0; // Start SPI communication
SPI_RW(0x00|W_REGISTER); // Select register 0x00 and indicate a write operation
SPI_RW(0x40); // Write 1 byte
SPI_RW(0x4B); // Write 1 byte
SPI_RW(0x01); // Write 1 byte
SPI_RW(0xE2); // Write 1 byte
CSN = 1; // Set CSN high (end SPI communication)
// Write predefined value 0xC04B0000 to register 0x01
CSN = 0; // Start SPI communication
SPI_RW(0x01|W_REGISTER); // Select register 0x01 and indicate a write operation
SPI_RW(0xC0); // Write 1 byte
SPI_RW(0x4B); // Write 1 byte
SPI_RW(0x00); // Write 1 byte
SPI_RW(0x00); // Write 1 byte
CSN = 1; // Set CSN high (end SPI communication)
// Write predefined value 0xD0FC8C02 to register 0x02
CSN = 0; // Start SPI communication
SPI_RW(0x02|W_REGISTER); // Select register 0x02 and indicate a write operation
SPI_RW(0xD0); // Write 1 byte
SPI_RW(0xFC); // Write 1 byte
SPI_RW(0x8C); // Write 1 byte
SPI_RW(0x02); // Write 1 byte
CSN = 1; // Set CSN high (end SPI communication)
// Write predefined value 0x99003941 to register 0x03
CSN = 0; // Start SPI communication
SPI_RW(0x03|W_REGISTER); // Select register 0x03 and indicate a write operation
SPI_RW(0x99); // Write 1 byte
SPI_RW(0x00); // Write 1 byte
SPI_RW(0x39); // Write 1 byte
SPI_RW(0x41); // Write 1 byte
CSN = 1; // Set CSN high (end SPI communication)
// Write predefined value 0xD99E860B to register 0x04
CSN = 0; // Start SPI communication
SPI_RW(0x04|W_REGISTER); // Select register 0x04 and indicate a write operation
SPI_RW(0xF9); // Write 1 byte
SPI_RW(0x9E); // Write 1 byte
SPI_RW(0x86); // Write 1 byte
SPI_RW(0x0B); // Write 1 byte
CSN = 1; // Set CSN high (end SPI communication)
// Write predefined value 0x24067FA6 to register 0x05
CSN = 0; // Start SPI communication
SPI_RW(0x05|W_REGISTER); // Select register 0x05 and indicate a write operation
SPI_RW(0x24); // Write 1 byte
SPI_RW(0x06); // Write 1 byte
SPI_RW(0x7F); // Write 1 byte
SPI_RW(0xA6); // Write 1 byte
CSN = 1; // Set CSN high (end SPI communication)
// Write predefined value 0x00731200 to register 0x0C (in reversed order!)
CSN = 0; // Start SPI communication
SPI_RW(0x0C|W_REGISTER); // Select register 0x0C and indicate a write operation
SPI_RW(0x00); // Write 1 byte
SPI_RW(0x12); // Write 1 byte
SPI_RW(0x73); // Write 1 byte
SPI_RW(0x00); // Write 1 byte
CSN = 1; // Set CSN high (end SPI communication)
// Write predefined value 0x0080B436 to register 0x0D (in reversed order!)
CSN = 0; // Start SPI communication
SPI_RW(0x0D|W_REGISTER); // Select register 0x0D and indicate a write operation
SPI_RW(0x36); // Write 1 byte
SPI_RW(0xB4); // Write 1 byte
SPI_RW(0x80); // Write 1 byte
SPI_RW(0x00); // Write 1 byte
CSN = 1; // Set CSN high (end SPI communication)
/* Data is already written to RFM70
// Write predefined value 0x404B01E2 to register 0x00 (in reversed order!)
CSN = 0; // Start SPI communication
SPI_RW(0x0E|W_REGISTER); // Select register 0x0E and indicate a write operation
SPI_RW(0x41); // Write 1 byte
SPI_RW(0x20); // Write 1 byte
SPI_RW(0x08); // Write 1 byte
SPI_RW(0x04); // Write 1 byte
SPI_RW(0x81); // Write 1 byte
SPI_RW(0x20); // Write 1 byte
SPI_RW(0xCF); // Write 1 byte
SPI_RW(0xF7); // Write 1 byte
SPI_RW(0xFE); // Write 1 byte
SPI_RW(0xFF); // Write 1 byte
SPI_RW(0xFF); // Write 1 byte
CSN = 1; // Set CSN high (end SPI communication)
*/
}