• Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

Reduce ISR Latency - Code Optimize

Status
Not open for further replies.

Suraj143

Active Member
I want to send 48 bytes from Bank 2 & 3 to 74HC595.Bytes must send in this order.
6fh,6B,67,63,5F

The code works the problem is this takes almost 5mS time to feed the 595's which is too long.
I want to compact my code to minimize ISR latency.

I use PIC16F88 - 4Mhz

Code:
ISR   
   -----
   -----
   movlw     0EFh            ;send Bank3 GPR 24 no's
   call       Load_S_FSR
   movlw     6Fh             ;send Bank2 GPR 24 no's
   call       Load_S_FSR
   goto     Make_Latch

Load_S_FSR   
   movwf     S_FSR
   movlw     .24
   movwf     Counter
   bsf       STATUS,IRP
   
Setup_Feed   
   movf     S_FSR,W
   movwf     FSR
   movf     INDF,W
   movwf     Temp
   movlw     .8
   movwf     Bit_Counter
  ;
Do_Feed_Loop   
   bcf       STATUS,C
   rlf         Temp,F   
  ;
Load_Shift_Reg   
   btfsc      STATUS,C
   
Set_Data_Pin   
   bcf       SR_Data       ; set "DATA"
   btfss     STATUS,C
   bsf       SR_Data       ; clear "DATA"
   nop
Make_Clock   
   bsf       SR_Clock       ; "CLOCK" Low to High Transition
   nop
   bcf        SR_Clock       ; //
  ;
   decfsz     Bit_Counter,F
   goto     Do_Feed_Loop   
  ;
Do_Next_Byte   
   movlw     .4
   subwf     S_FSR,F
   decfsz     Counter,F
   goto     Setup_Feed
   bcf        STATUS,IRP
   return
 
Last edited by a moderator:

granddad

Well-Known Member
Is there a reason you dont want to run pic at 8 Mhz internal or higher with external xtal , or you could reduce the calls ...
Edit
Are you context saving in the ISR
Where is make_latch
 
Last edited:

Mike - K8LH

Well-Known Member
Do you have 48 74HC595 devices daisy chained together? Please tell us what you're doing?
 
Last edited:

Suraj143

Active Member
Yes I have 48 74HC595 devices daisy chained together.

In my design I use all 192 bytes, 96 bytes from each (Bank 2 & 3). But from this 96 bytes I use only 24 bytes & from both banks I use 48 bytes. (Other bytes contains some other data).

In simply I want to load 48 data bytes 24 each from bank 2 and bank 3.

Load bank2 bytes -----> 16Fh, 16B, 167...... 113h (24th byte)
Load bank3 bytes------>1EFh, 1EB ..... 193h (24th byte)

Those bytes have an address gap of 4 bytes. I think now you will have a clear idea.
 
Last edited:

Suraj143

Active Member
Hi mike.i have no any extra pins.if you really need then i can shift to a 28 pin pic.but i like to restrict to a 18 pin pic.

Sorry no schematic.

from pic side pins

Serial data
Serial clock
Latch
Output enable
Rest of all are switches
 

Mike - K8LH

Well-Known Member
ok, but, what are you using these 384 output bits for, if you please?

what kind of speed do you need? you can get it down from ~5189 usecs (13.5 cycles per bit) to about ~2140 usecs (5.6 cycles per bit) by modifying the code but will that be satisfactory? If you had a spare 8-bit port you could modify the hardware slightly and load eight 74HC595 ICs at a time with eight clock pulses (pseudo 8-channel SPI) and get it down to around ~1000 usecs (2.6 cycles per bit). Not sure you could do much better than that with 384 serial data bits...

it would probably be better if you told us what you're trying to do. there may be better ways to accomplish the same thing... same with the schematic. you say you don't have any extra pins but perhaps there's a way to temporarily re-task existing pins to load the shift registers during the ISR. you say "the rest are switches"... how many is that? eight or nine? If so, they might easily be borrowed to load the shift registers...
 
Last edited:

Suraj143

Active Member
Brilliant, 2140us is more than enough for me.i like the software modification.

The leds are a still image.but it will change its shape according to the inputs.inputs are coming at 4ms time base.so before it arrives i must update the image.
 

Mike - K8LH

Well-Known Member
.... 2140us is more than enough for me.
Try this...
Code:
        radix   dec
ISR
   ...
   ...
        bsf     STATUS,IRP      ; indirect access to banks 2 & 3
        movlw   0xEF            ; send Bank3 GPR 24 no's
        call    Load_S_FSR      ;
        movlw   0x6F            ; send Bank2 GPR 24 no's
        call    Load_S_FSR      ;
        bcf     STATUS,IRP      ; indirect access to banks 0 & 1
        goto    Make_Latch      ;

Load_S_FSR
        movwf   FSR             ;
        movlw   24              ;
        movwf   Counter         ;
        movlw   4               ;
nxtbyte
        bcf     SR_Data         ; bit 7
        btfss   INDF,7          ;
        bsf     SR_Data         ;
        bsf     SR_Clock        ;
        bcf     SR_Clock        ;
        bcf     SR_Data         ; bit 6
        btfss   INDF,6          ;
        bsf     SR_Data         ;
        bsf     SR_Clock        ;
        bcf     SR_Clock        ;
        bcf     SR_Data         ; bit 5
        btfss   INDF,5          ;
        bsf     SR_Data         ;
        bsf     SR_Clock        ;
        bcf     SR_Clock        ;
        bcf     SR_Data         ; bit 4
        btfss   INDF,4          ;
        bsf     SR_Data         ;
        bsf     SR_Clock        ;
        bcf     SR_Clock        ;
        bcf     SR_Data         ; bit 3
        btfss   INDF,3          ;
        bsf     SR_Data         ;
        bsf     SR_Clock        ;
        bcf     SR_Clock        ;
        bcf     SR_Data         ; bit 2
        btfss   INDF,2          ;
        bsf     SR_Data         ;
        bsf     SR_Clock        ;
        bcf     SR_Clock        ;
        bcf     SR_Data         ; bit 1
        btfss   INDF,1          ;
        bsf     SR_Data         ;
        bsf     SR_Clock        ;
        bcf     SR_Clock        ;
        bcf     SR_Data         ; bit 0
        btfss   INDF,0          ;
        bsf     SR_Data         ;
        bsf     SR_Clock        ;
        bcf     SR_Clock        ;
        subwf   FSR,F           ; setup for next byte (FSR -= 4)
        decfsz  Counter,F       ; last byte? yes, skip, else
        goto    nxtbyte         ; branch (do next byte)
        return                  ;
 
Last edited:

Jon Wilder

Active Member
I write really tight ASM code but Mike is the master of it. I probably picked up a few tricks from him early on.
 
Status
Not open for further replies.

Latest threads

EE World Online Articles

Loading
Top