;*** SPI ***
; MAKE SDI TRIS BIT AN INPUT!
;{
;SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER
bsf STATUS,RP0 ; Bank 1
bsf SSPSTAT,SMP ; 1 = Input data sampled at end of data output time ( Master Mode)
bsf SSPSTAT,CKE ; 1 = Transmit occurs on transition from active to Idle clock state
bcf SSPSTAT,BF ; 1 = Receive complete, SSPBUF is full
bcf STATUS,RP0 ; Bank 0
;SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER
movlw b'00000010' ; = SPI Master mode, clock = OSC/64
movwf SSPCON
bcf SSPCON,WCOL ; 1 = An attempt to write the SSPBUF register failed because the SSP module is busy ; (must be cleared in software)
bcf SSPCON,SSPOV ; 1 = A new byte is received while the SSPBUF register is still holding the previous data
bsf SSPCON,CKP ; 1 = Transmit happens on falling edge, receive on rising edge. Idle state for clock is a high level.
bsf SSPCON,SSPEN ; 1 = Enables serial port and configures SCK, SDO and SDI as serial port pins
;***
movlw .99 ;random
movwf SSPBUF
bsf STATUS, RP0 ; ; Bank 1
btfss SSPSTAT, BF ; Has data been received (transmit complete)?
goto $-1 ; No
bcf STATUS, RP0 ; Specify Bank0
;}