Range type in VHDL?

[bmcculla]

I was wondering if there is a way to specify a range constant in VHDL?

I'm trying to make a generic microcontroller memory bus interface. I want to be able to change the data width and address width easily. To support bigendian and little endian processors I need to be able to pass a range as a generic into entities (support (7 downto 0) and (0 to 7)). It would be nice just to be able to pass the whole range in as a constant. anyone have ideas about how to do this?

Thanks
Brent