Questions Regarding Look Up Tables

[mawais826]

Hi, I hope all members are doing well.
I would like to ask a couple of of questions regarding look up tables.
1) how can we create 2-1 multiplexer using only 2 input look up tables?
2) can outputs of one set of look up tables be used to map SRAM bits of another look up table?
Any help is much appreciated.

 

[Pommie]

Your questions make no sense. Try describing what you are trying to do.

Mike.

 

[mawais826]

Hi Mike,
I am trying to implement a Four Input LUT using only two input LUTs.

 

[Pommie]

I've still got no idea what you're trying to do.

Mike.

 

[mawais826]

I am trying to figure out that if an FPGA has only two input Look up tables available how would one use that FPGA's two input look up tables to implement 4 variable function?

 

[mawais826]

Sorry if I am not being clear. Let me provide some pictures. Attached is picture and link of how we can realize 3 variable function using 2 input LUT's but i am not able to understand how this solution was derived.
https://electronics.stackexchange.c...e-input-lut-if-i-have-a-lot-of-two-input-luts

 

[rjenkinsgb]

How many inputs (total bits over the four values) and what size result?
A look-up table is, in essence, just a area of memory with the address range being the total number of input bits.

One with two 8-bit inputs needs 2^16 = 65536 bytes or words; 64K.
eg. If you wanted four, 5 bit inputs that is 2^20 possibilities or 1MByte of storage.

For single-bit inputs, which part of the article you link implies, then four LUTs all fed by the first two inputs and a four-way multiplexer controlled by the other two inputs to select the correct result combination.

 

[danadak]

How to implement a three-input LUT if I have a lot of two-input LUTs?

I have gone through various sources... But I am not quite sure what it is. For example, I have three input variables: A, B and C. Now I have to use two 2-input LUTs such that their input lines are

electronics.stackexchange.com

What is an LUT in FPGA?

I have gone through various sources... But I am not quite sure what it is.I want an and gate and the logical equivalent is two inputs feeding to one gate and for Y=AB' the logical equivalent is fee...

electronics.stackexchange.com

Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount...

www.hindawi.com

Regards, Dana.