puzzling output

Maybe someone can help here...

**broken link removed**

U2 and U3 are LS590 8 bit counters with registers.

I need a 32 µs pulse output. I am cascading two counters. Each has a 10MHz clock. It takes 320 clock cycles to make 32 µs. So, the counters count to 320. The bits that make 320 in binary are AND'd and that output resets the timers and the SR- latch.

For the most part I have a nice 32 µs pulse output. However, the pulse duration seems to jump around between 3 values. The first is 32 µs, the next is 26 µs, and the last is 6.28 µs. The values are seemingly random.

[EDIT] I know the outputs clear as well because the AND gate drops out. Still the same problem though.

Any ideas?

Sorry for the schematic... I cant find a decent computer based program to let me draw them.

Glitch

I think I may have messed up my post so here is a new one.
The reset pulse will be very short and may not always reset both counters. This would give you the times you discussed 32 usec. ok both reset. 6.4 usec, 1st timer not reset, 26 usec, second timer not reset. I think you could move the reset to the latch and get them both for sure.
Be real easy with a scope. Hopr this is it.

Thanks for the reply.

The reset pulse is one clock cycle (100 ns). I considered this possibility and did the math with each timer not being reset. The math does not add up to the values I'm getting. Of course I could be doing it wrong!

I'll dig into this idea more with a scope at work tomorrow. Thanks again for the reply.

BTW: I should mention that I built this on a breadboard before redoing it on a perf board with wire wrapping. It worked flawlessly on the breadboard.

It seems an unlikely coincidence that one counter is counting to 25.6uS and the second to 6.4uS. I think ronv is correct and only 1 counter is being reset.

Mike.

Pommie said:

It seems an unlikely coincidence that one counter is counting to 25.6uS and the second to 6.4uS. I think ronv is correct and only 1 counter is being reset.

Mike.

Click to expand...

You're right... it is an unlikely coincidence. I'll check more into that today.

How is the supply?
Is it clean and stable?
Is it adequately decoupled? As a minimum, you need a 0.1uF capacitor to provide high frequency decoupling, preferably one capacitor at each IC.

JimB

ronv said:

I think I may have messed up my post so here is a new one.
The reset pulse will be very short and may not always reset both counters. This would give you the times you discussed 32 usec. ok both reset. 6.4 usec, 1st timer not reset, 26 usec, second timer not reset. I think you could move the reset to the latch and get them both for sure.
Be real easy with a scope. Hopr this is it.

Click to expand...

You were right. I ended resetting the counters with a one shot.

Thanks!