PSRAM design guidelines

Hello forum,

First time poster here. I've been searching for some design guidelines or reference designs for PSRAM layout routing. I've routed DDR RAMs before and they have some pretty harsh length matching and impedance control requirements and i would like to know if PSRAM have some kind of special layout recommendations.

I've become a little paranoid with rise times after studying high speed design.

Any help would be awesome.

EDIT: I'm interfacing it to a FPGA EP2C5.