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PSPICE schematic (full-bridge inverter)

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MsStateDawg

New Member
I have been working on a full-bridge inverter in Pspice for quite some time now. My goal is to use PWM at 18 kHz. I have used two 741 op-amps as comparitors to compare a 60 Hz sine wave with a 18 kHz sawtooth wave. The result, when filtered correctly, should give a 60 Hz output.

Here is a link to the circuit setup and the waveform I am getting:

**broken link removed**

**broken link removed**

The problem is that the output will only increase to 20 volts (peak-to-peak). I realize the schematic only has 10 volts as the source. However, the problem occurs with any voltage greater than 10 volts. I'm almost positive that the two upper bransistors have to be connected from gate to source. Does anyone know how this can be done using the op-amps? Is there any other possible way?

I also have PSPICE schematic located at the following link:

**broken link removed**

I greatly appreciate any help.
 

Roff

Well-Known Member
You have two things contributing to this situation:

1. When the 741 output is high, it will only get within 1 or 2 volts of Vcc. In your circuit, this means it will get to around 11-12v.

2. M62 and M64 are source followers. The source will only go as high as the gate, minus a couple of volts ( the exact value is dependent on the characteristics of these MOSFETs. Remember that, in order to turn on a MOSFET, Vgs must be greater than the threshold voltage.

The easiest solution is to change M62 and M64 to p-channel MOSFETs, and change the phases of their gate drives (f to M62 gate, c to M64 gate). The voltage on the gate needs to go to the positive rail (10v in your schematic) to turn them off. If you increase the 10v supply, you have to increase Vcc.

The 741 is not suitable for driving monster MOSFETs. That transistor has a gate capacitance of 3700pF, and each 741 is driving 2 of them. The 741 output is limited to about 25ma. Dv/dt=I/C, which means your gate slew rate (SR) is going to be

SR=2.5e-2/(2*3.7e-9),
SR=3.4v/usec (Due to Miller effect, it will be slower, but this illustrates the point).
This means it will take several microseconds for your transistors to completely switch. At 10% duty cycle, your pulse width is only 5.6usec. The transistor dissipates a lot of power during switching, so you need to minimize gate rise and fall times.
You should also probably consider having some dead time (100ns?) between c and f. otherwise, you potentially have short periods of time where you have both transistors on one side of the bridge conducting.

You need two rail-to-rail drivers for your bridge, and they each need to be able to source and sink several amps transient current.
 

Styx

Active Member
as stated above change to a P-N type legs that will sort alot of yr probs - this will only work upto a DC link bus of upto the Opamp

For higher vlotages think abt making a kind of floating gate drv - then you can use all N-types

Try putting a NPN-PNP push-pull output stage to act as a gate drive to the MOSFETS. Also why not use a proper comparator the LM111 is pretty good comparator that comes with SPICE.
 

RUp

New Member
Pspice simulation of Phase shifted full bridge inverter

Sir
I have been simulating the full bridge with auxiliary inductors attached at each leg of the bridge to see ZVS .The crossing of voltage and current occurs at 40% of full load current which is not acceptable. Kindly suggest me what can I do .
 

vwdevotee

New Member
Hi. I'm also trying to simulate a full bridge DC DC converter in PSpice but can't figure out how to trigger the PWM of the FETs on the high side. Can you repost your schematic file or point me to a good description? I've just started using Pspice today.
 

vwdevotee

New Member
Hi. I'm also trying to simulate a full bridge DC DC converter in PSpice but can't figure out how to trigger the PWM of the FETs on the high side. Can you repost your schematic file or point me to a good description? I've just started using Pspice today.
 

cnyryy

New Member
Hi,

Help needed, i'm simulating full bridge inverter in pspice as well but i'm having problem with my full bridge bridge inverter circuit with the switching model. The waveform of the full bridge was not as aspected.

Below is the Vpulse setting that i set for my full bridge to operate :
V1=0, v2=15 td= 1n tr=1n tf=1n pw=5u per= 10u (this setting same for all 4 switches)

I check waveform at Vp( transformer primary) but i just manage to get it correctly.

Can anyone advice me on this?

Appreciate..
 

ericgibbs

Well-Known Member
Most Helpful Member
Hi,

Help needed, i'm simulating full bridge inverter in pspice as well but i'm having problem with my full bridge bridge inverter circuit with the switching model. The waveform of the full bridge was not as aspected.

Below is the Vpulse setting that i set for my full bridge to operate :
V1=0, v2=15 td= 1n tr=1n tf=1n pw=5u per= 10u (this setting same for all 4 switches)

I check waveform at Vp( transformer primary) but i just manage to get it correctly.

Can anyone advice me on this?

Appreciate..

hi
Please post your 'asc' file so that we can run it.
 

ericgibbs

Well-Known Member
Most Helpful Member
Hi ericgibbs,

Can i send the circuit to you email?

Thank.

Appreciated.

hi,
It would be best if you posted the file to this thread, it would give other members of the Forum the opportunity to participate.
 

cnyryy

New Member
Hi,

Below is the net list file from my simulation.I'm not sure how to attach the full file here since i'm quite new to this forum.


* source FULL BRIDGE
V_V4 N9104305 N9062553
+PULSE 0 15 5u 1n 1n 2.5u 10u
V_V2 N9069305 0
+PULSE 0 15 5u 1n 1n 2.5u 10u
V_V5 N17948 0 100
D_D4 N9062574 N9051332 MUR150
L_L5 N9051332 VOUT 500u
C_C4 VOUT 0 50u IC=75 TC=0,0
D_D5 N9061729 N9051332 MUR150
X_TX1 N9069868 N9062553 N9062574 0 N9061729 XFRM_NONLIN/CT-SEC PARAMS:
+ LP_TURNS=50 LS1_TURNS=5 LS2_TURNS=5 COUPLING=.99 RP_VALUE=0.5 RS_VALUE=0.5
X_M8 N9069868 N9069305 0 mmft3055vl/ON
X_M10 N17948 N9104305 N9062553 mmft3055vl/ON
X_M11 N9062553 N17804 0 mmft3055vl/ON
C_C6 N17948 N9062553 1n IC=75 TC=0,0
C_C7 N9062553 0 1n IC=75 TC=0,0
C_C8 N9069868 0 1n IC=75 TC=0,0
C_C9 VOUT 0 50u IC=75 TC=0,0
D_D7 0 N9069868 MUR150
D_D8 N9062553 N17948 MUR150
D_D9 0 N9062553 MUR150
R_R1 0 VOUT 10 TC=0,0
D_D10 N9069868 N17948 MUR150
C_C10 N17948 N9069868 1n IC=75 TC=0,0
X_M12 N17948 N9107527 N9069868 mmft3055vl/ON
V_V3 N17804 0
+PULSE 0 15 5u 1n 1n 2.5u 10u
V_V6 N9107527 0
+PULSE 0 15 5u 1n 1n 2.5u 10u

V6 and V4 is the Vpulse for Upper FET. i suspect the connection might not right.Furthermore, how i can i use TL494 modelling in PSPICE for this simulation
 
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