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Problem using TMRO to gate TMR1 as Counter

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jpanhalt

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Chip: Enhanced mid-range (16F1829)
Environment: MPLab 8.92
Language: MPASM

Actually, this is a (another) pseudo-problem using MPLab SIM with a peripheral that won't simulate properly. I wanted to use TMR1 to count TMRO rollovers to get a long-period interrupt that would run relatively independent of the rest of the program. Setting up TMR0 is simple. It is done mostly with the OPTION_REG. No prescale was used, and bit<4> was set to increment on low-to-high transition. Setting up TMR1 is done mostly with T1CON and TIGCON. The descriptions could be a little clearer -- make that a lot clearer in the case of T1CON, bits 6-7 (i.e., TMR1CS). Hence, this post.

The problem was that when set correctly, TMR1 does not increment properly in simulation with MPLab SIM. It wasn't until after much searching and testing that I decided to do hardware simulation with an ICD3. It worked immediately.

Here are the settings for each register that worked:

T1CON: b'01000101'
Comment:
1) Bit<2> when set does not synchronize with an external clock input. I was using the internal oscillator for these tests and changing bit<2> made no noticeable difference.
2) Other sources suggest setting bit<7>, but those sources were using 16Fxxx chips. When bit<7> is set and bit<6 >is set or clear, it simply doesn't work.

T1GCON:b'11000001'
NB:Bit<6> is set, which means TMR1 counts only when its gate (controlled by TMR0)is high (i.e, during rollover).

This subject has been addressed on Stack Exchange (
https://electronics.stackexchange.c...-timer0-overflow-to-gate-timer1-on-pic12f1822 ). However, that discussion does not mention the need to do hardware simulation instead of relying on MPLab SIM.

Regards, John
 
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