It can be a wide range of topics. At a high level architecture it can be the planning for sleep and active sections of the chip. For example, to save power the dynamic memory controller may have available time slots where the clocking of the logic can be suspended. The newest i3,i5,i7 series do a lot of this.
Deep sub-micron high speed CMOS, <45 nm, devices have a high leakage current. To prevent excessive power dissipation on chip, circuit blocks are literally disconnected from the power bus when possible to save power. Obviously when this is done any static register values are lost. There can be a shadow higher Vp (gate threshold voltage) device register which has lower standby current drain but too slow to operate at full clocking speed that saves the high speed register states before section is powered down. Upon wake up, the standby registers are automatically used to return the register states to the high speed registers.
It can be planning and simulation of power grid to various sections of the chip to ensure maximum supply voltage drop to each section is within acceptable limits to ensure logic makes it operating clocking speed. Again for deep sub-micron devices, the power supply voltage can only be a maximum of 1.35 vdc and the logic may not make its required speed if voltage drops below 1.1 vdc so there is a narrow range of supply voltage that must be maintained.