I designed a Power Amplifier which I drew its schematic below. View attachment 67036
The Input Power is constant, and I control the Power Gain of the PA by changing the values of IREF1 and IREF2 (controllable Current Sources).
When I decrease IREF1 & I REF2, the Power Gain decreases as well (which is what I wanted to achieve), but also the Efficiency of the Power Amplifier decreases.
When I decrease VDD (shown in Schematic) in parallel to decreasing IREF1 & IREF2, the Efficiency drops less drastically.
Please see Efficiency Graph below with Constant VDD Vs. Regulated VDD - as function of the Power Gain. View attachment 67037
The first thing I'm trying to achieve is understanding why the Efficiency decreases as IREF1 & IREF2 decrease, with Constant VDD.
Can you please share some wisdom and guidelines regarding the Efficiency decrease?
Hi and thanks for your comments - please find answers below.
1. MN is an ideal Matching Network - one to match input source (RF_IN) with PA and one to match PA with Load. ISM is an ideal Inter-Stage Matching Network that matches the two stages.
2.
I assume no power losses in the Matching Networks (MN & ISM) - They are considered to be ideal.
3.
I define Efficiency as Drain Efficiency = AC Output Power / DC Power
Where: AC Output Power = RMS{AC Output Current * AC Output Voltage} (i.e. the current and voltage delivered to the Load; No DC Signal is transferred to the load). DC Power = VDD * (Idrain) [ Idrain = ICE(BJT1) + ICE(BJT2) ]
A simulation in LTSpice confirms efficiency decreases with decreasing bias current. IMO this is due to the resistance of the base-emitter junctions decreasing as the bias current increases. Reduced resistance leads to increased RF current from the source.