PORTB Mismatch behavior

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micropad

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Dear All,

PortB Change interrupt may continue interrupt until clear the mismatch behavior

It would be much appreciated if some one can teach me, how mismatch behavior occurred at the portb using attache picture

Thanks in advance
View attachment 68606
 
The schematic you attached in your original post doesn't show the IOC logic.

IOC isn't available on all I/O pins but where it is it looks like the highlighted section in the attached schematic. Q1 and Q3 are the internal instruction clock phases

https://ww1.microchip.com/downloads/en/devicedoc/33023a.pdf

Worth looking at Section 4.2 (Clocking Scheme/Instruction Cycle) and 9.3 (PORTB and the TRISB Register)
 
Last edited:
Dear Geko,
Thanks for the reply

I think the PIC 18F architecture dose not have mismatch condition occur, Am I correct?

Thanks in advance
 
micropad said:
Dear Geko,

I think the PIC 18F architecture dose not have mismatch condition occur, Am I correct?
Click to expand...

If you mean doesn't have Interrupt-on-Change?

Yes they do - check the datasheets and don't stop at the first port schematic you find - Port B 4-7 have IOC logic.
 
Dear Geko,
Really thanks for the reply
I need to know is when the portb change interrupt is occurred in the PIC18F , is it necessary to clear the mismatch condition?

Please advice
 
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