Output register stores the data temporarily from display data RAM when CS1B, CS2B, CS3 is in active mode and R/W and
RS=H, stored data in display data RAM is latched in output register. When CS1B to CS3 is in active mode and R/W=H, RS=L,
status data (busy check) can read out.
To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in display data RAM
is latched into output register. In second access, MPU can read data which is latched. That is, to read the data in display data
RAM, it needs dummy read. But status read is not needed dummy read.