;
; the counter input is gated off after 200-msecs, now finalize
; our 32-bit count accumulator
;
; ACCA+0, Most significant byte (TMR0 overflows)
; ACCA+1, Next significant byte (TMR0 overflows)
; ACCA+2, copy of TMR0 register
; ACCA+3, prescaler, Least significant byte
;
movf TMR0,W ; get TMR0 value |B0
movwf ACCA+2 ; |B0
;
; empty the 1:256 prescaler by toggling the TMR0 edge select
; bit and decrementing ACCA+3 (initially 00) until detecting
; the prescaler overflow into TMR0.
;
FLUSH bsf STATUS,RP0 ; select Bank 1 |B1
bcf OPTION_REG,T0SE ; clock on rising edge |B1
bsf OPTION_REG,T0SE ; clock on falling edge |B1
bcf STATUS,RP0 ; select Bank 0 |B0
decf ACCA+3,f ; decrement counter LSB |B0
movf TMR0,W ; compare TMR0 to saved value |B0
xorwf ACCA+2,W ; prescaler overflow? |B0
bz FLUSH ; no, clock it again |B0
;