nickelflippr
Member
Have been playing with some Pic I2c Master to Pic Slave code. When the Pic master sends a read to the slave, a peripheral interrupt flag is set and an ISR is started to feed the slave SSPBUF with data. Meanwhile, the slave main code is constantly updating the registers at a regular interval.
The problem arises when eventually the master and slave become out of sync, with new data corrupting a previous array of data to be sent. I am new to interrupts, so not sure how to go about some code that might keep the the master and slave in sync, or avoiding a slave write while the master is reading.
Maybe the answer is very careful delays being set forth, in both the master and slave units, so collision is avoided? Thanks for any ideas.
P.S. The Pic slave is sharing the master Vdd, Vss, and have seperate, but equal 20mhz oscillators. Also, the slave is attached by about a foot of I2C wire.
The problem arises when eventually the master and slave become out of sync, with new data corrupting a previous array of data to be sent. I am new to interrupts, so not sure how to go about some code that might keep the the master and slave in sync, or avoiding a slave write while the master is reading.
Maybe the answer is very careful delays being set forth, in both the master and slave units, so collision is avoided? Thanks for any ideas.
P.S. The Pic slave is sharing the master Vdd, Vss, and have seperate, but equal 20mhz oscillators. Also, the slave is attached by about a foot of I2C wire.