PIC Architecture

[asmpic]

Can someone help explain what needs to be done for this problem?

Write a timing diagram, including values of the PC(program counter), for the following instruction sequence when (a) the BTFSC instruction results in a skip and (b) when it does not.

Address Instruction
50 BTFSC
51 ADDLW
52 SUBLW

All I know is that I need to show when each instruction Fetches and Executes, but I don't understand what the program counter is.

 

[TheOne]

PC keeps track of which instruction should be executed next.

 

[asmpic]

PC keeps track of which instruction should be executed next.

Right, but then why is the PC somethings like 50 50 50 50 51 51? How do you figure out how many times it should Fetch or execute an instruction?

 

[TheOne]

It contains a program byte of opcodes and operands. Opcode instructs what to do and operand say where in memory.

https://www.hyperdictionary.com/dictionary/program+counter

 

[bonxer]

The program counter keeps track of which instruction is next to be executed. See the PIC 16F877 data sheet, section 2.3 for a detailed description of PCL and PCLATH.

Basically, when your program runs, the next instruction's memory locaton is automatically loaded while the current instruction is being executed. Assume the program has been run up until instruction number 0049. At this point, the PC contains 0050. This lets the microcontroller know where the next instruction is that it fetches from memory to execute. So 0049 is done. The PIC asks "Where is the next instruction?" It looks at the PC, sees the value 0050, and loads whatever command is there, in this case:

BTFSC

That instruction is Bit Test F Skip if Clear. If the specified bit is clear (0), it will skip over the next instruction, and take two cycles to execute, since it will have to load a new memory location to skip to. If the bit is set (1), the next memory location was already automatically set, so it continues normally and only takes single cycle to execute, just like every other command.

So we will make two run throughs of the code. In the first case the bit is set (1), so things will flow normally. In the second case, the bit is clear (0), which will change things:

Case 1, bit is set (1):

00xx Previous executes.  Time unknown.    PC = 0050
0050 BTFSC    executes.  Time = 1 cycle.  PC = 0051
0051 ADDLW    executes.  Time = 1 cycle.  PC = 0052
0052 SUBLW    executes.  Time = 1 cycle.  PC = 0053

Case 2, bit is clear (0):
00xx Previous executes.  Time unknown.    PC = 0050
0050 BTFSC    executes.  Time = 2 cycle.  PC = 0052  (1 to execute, 1 to change PC)
0052 SUBLW    executes.  Time = 1 cycle.  PC = 0053

Does this answer your question?

 

[asmpic]

The program counter keeps track of which instruction is next to be executed. See the PIC 16F877 data sheet, section 2.3 for a detailed description of PCL and PCLATH.

Basically, when your program runs, the next instruction's memory locaton is automatically loaded while the current instruction is being executed. Assume the program has been run up until instruction number 0049. At this point, the PC contains 0050. This lets the microcontroller know where the next instruction is that it fetches from memory to execute. So 0049 is done. The PIC asks "Where is the next instruction?" It looks at the PC, sees the value 0050, and loads whatever command is there, in this case:

BTFSC

That instruction is Bit Test F Skip if Clear. If the specified bit is clear (0), it will skip over the next instruction, and take two cycles to execute, since it will have to load a new memory location to skip to. If the bit is set (1), the next memory location was already automatically set, so it continues normally and only takes single cycle to execute, just like every other command.

So we will make two run throughs of the code. In the first case the bit is set (1), so things will flow normally. In the second case, the bit is clear (0), which will change things:

Case 1, bit is set (1):

00xx Previous executes.  Time unknown.    PC = 0050
0050 BTFSC    executes.  Time = 1 cycle.  PC = 0051
0051 ADDLW    executes.  Time = 1 cycle.  PC = 0052
0052 SUBLW    executes.  Time = 1 cycle.  PC = 0053

Case 2, bit is clear (0):
00xx Previous executes.  Time unknown.    PC = 0050
0050 BTFSC    executes.  Time = 2 cycle.  PC = 0052  (1 to execute, 1 to change PC)
0052 SUBLW    executes.  Time = 1 cycle.  PC = 0053

Does this answer your question?

I'm understanding it a little better now. Now what about the fetching? When does the PC fetch the instruction to be executed?

The way me teacher has done it is like the following:

PC:       10  11  11  11  11  12  12  40  40  41  41  41  41  41  42  11
call:     F    F   F   F   E   E   E  E
addlw:                     F   F  F  F

return:                                    F   F   F   F   E   E   E    E
sublw:                                                     F   F   F    F

for the following set of instructions:
10 call 40
11 addlw
.
.
40 return
41 sublw

 

[bonxer]

As your timing diagram there demonstrates, the next instruction is fetched while the current instruction is executing. That's why instructions only take one cycle. 1 cycle = fetch & execute. That way when it is done executing one instruction, it is already ready to proceed to the next. When it's done with that one, the next one's ready. It's only whenever you have a jump occuring that this changes. A GOTO or a BTFSS and stuff will do that. When they are first entered and are about to execute, the following instruction is being fetched. But when the chip finds the fact that a jump is necessary, the next instruction that it has ready to go is no longer valid. It has to load the specified instruction, hence the additional cycle.

 

[asmpic]

Would this be correct for when the bit=1

PC:		50  50  50  50  51  51  51  51  52  52  52  52
BTFSC:	 F   F   F   F   E   E   E   E
ADDLW:		              F   F   F   F
SUBLW:				                        F   F   F   F

 

[bonxer]

I don't understand your original timing diagram exactly. I am guessing you are paraphrasing what your instructor gave on the board? The PIC takes four oscillator ticks for one instruction cycle, so that is my assumption. Each of your instruction cycles should be four ticks at the top bar there, as opposed to five here, two there, etc.

 

[bonxer]

Would this be correct for when the bit=1

PC:		50  50  50  50  51  51  51  51  52  52  52  52
BTFSC:	 F   F   F   F   E   E   E   E
ADDLW:		              F   F   F   F
SUBLW:				                        F   F   F   F

Close. But you forgot to show that ADDLW is being executed as SUBLW is being fetched.

 

[asmpic]

Would this be correct for when the bit=1

PC:		50  50  50  50  51  51  51  51  52  52  52  52
BTFSC:	 F   F   F   F   E   E   E   E
ADDLW:		              F   F   F   F
SUBLW:				                        F   F   F   F

Close. But you forgot to show that ADDLW is being executed as SUBLW is being fetched.

Oh, ok. I think I understand it now. So how would I show the extra cycle for when the bit=0?

 

[asmpic]

I don't understand your original timing diagram exactly. I am guessing you are paraphrasing what your instructor gave on the board? The PIC takes four oscillator ticks for one instruction cycle, so that is my assumption. Each of your instruction cycles should be four ticks at the top bar there, as opposed to five here, two there, etc.

The diagram I posted is exactly how my professor had it on the board...

 

[asmpic]

Would the timing diagram for bit=0 look something like this:

PC: 		50  50  50  50  51  51  51  51  52  52  52  52
BTFSC:	 F   F   F   F   E   E   E   E
BTFSC:			           F   F   F   F   E   E   E   E
SUBLW:					                     F   F   F   F

 

[bonxer]

This would be better for bit = 0:

PC:          50  50  50  50 | 51  51  51  51  | 52  52  52  52  | 53  53  53  53
xx Previous: E   E   E   E  |                 |                 |
50 BTFSC:    F   F   F   F  | E   E   E   E   | E   E   E   E   |
51 ADDLW:                   | F   F   F   F   |                 |
52 SUBLW:                   |                 | F   F   F   F   | E   E   E   E
53 Following:               |                 |                 | F   F   F   F
----------------------------|-----------------|-----------------|---------------
             Execute Prev.  | Execute BTFSC.  | Execute BTFSC.  | Execute SUBLW
             Fetch BTFSC.   | Fetch ADDLW     | ADDLW not next!!| Fetch Following
                            | in case it might| Perform jump by |
                            | be used next.   | Setting PC=52.  |
                            |                 | Fetch SUBLW.    |