• Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

Opinion on Decoupling

Status
Not open for further replies.

Gene

New Member
With all the talk recently about 4017 chips, I read on a web site that all unused outputs should be grounded and that all pin #16s (+V) should be fitted with a 47 - 100 mfd electrolytic cap for better operation. Any opinions on this?
 

Dean Huster

Well-Known Member
Baloney -- for the most part

Gene, as far as grounding the outputs go, DON'T. If the inputs naturally assume a state that forces an output to a HIGH, bad things will happen. It may be that the instructions were to ground unused INPUTS vs. outputs. The idea there is that it keeps the current draw a little lower.

Decoupling each +V pin with a massive cap like that is pointless. However, I feel that decoupling is one of the most important -- and neglected -- things that you can do. It's even more neglected when breadboarding circuits and a lot of circuit problems can be avoided if you use proper decoupling. But most decoupling problems, especially with digital circuits, have to do with higher frequencies, and the fat electrolytics don't deal with those well at all. Yes, decouple each +V pin, but do it with a 0.1µF or 0.01µF disc ceramic cap from +V to ground, one cap for each chip. The disc ceramic caps are better able to take care of those fast transients that get into the supply lines and cause false clocking or false resets and such with clocked logic.

If working with analog circuits, I prefer to decouple each +V and -V (if a negative supply and not ground) with a 10µF aluminum or tantalum electrolytic cap in parallel with a 0.1µF or 0.01µF disc ceramic cap.

Dean
 

bogdanfirst

New Member
if you looked at some circuits from digital type, you could see that around the chips there are one or more capacitors ceramic, usually, that are for filering. the explication is, in essence, simple: small value, non-electrolothic capacitors can block short-time spikes in the power suply.
large value capacitors are for long duration spikes, and they can block them, but dont act so fast.
so the idea is this: put a larger value electrolitic cap for the suply, and lots of ceramic capacitors around the board.
 

Gene

New Member
Thanks to all. The reason for the original question was that it did not make sense (at least to me) to put a large electrolytic capacitor on each (+) pin. In my circuit, the (+) goes from the power supply to pin #16 of each IC. Now, if I add a capacitor to each IC at the (+) pin - these will all be in parallel with the capacitor I used back in the power supply. That is, each electrolytic capacitor goes from (+) to ground and they are all in parallel. The reason the plan made no sense was that, while this idea may effectively decouple all the ICs, the filtering effect at the power supply is non-existant. The result would be clean running ICs but a ragged power supply. The idea of ceramic capacitors makes perfect sense, they are small on the circuit board, cheap, and available . . . and installed. . . and running smoothly.
 
Status
Not open for further replies.

Latest threads

EE World Online Articles

Loading
Top