? add an additional pull down resistor to outp , reduce that 33k atenuate with small resistor 10Ω and less before uC MOSFET input
?? add a feedback (e.g. a minor hysteresis) to your comparator biasing it as if it was an op amp ... reduces need to overdrive it with 13V SW ... ??? assume the input stage PN junctions have BW FW recovery as any diode . . .
the frequency 1/10milliseconds (100Hz) won't show the feature you describe in LTSpice LM393 and CD4049 (poor) component level models
the frequency 10mc (? mega cycles (per second)) . . . oh i forgot - the 39x can do bearly 2MHz
testing 10kc ... 100k ? too fast for 33kΩ
testing 100Hz with miread 33k : 3k3 ... k33 (330Ω) the comparator output stays at 1.9V that is above 1.1V simulated threshold
testing 100k with 3k3 pullup ... nope
...
adding parasitic inductance 2µH and 5pF capacitance to SW 5pF capacitance to +input (8.3V with 1k series resistance)
AND L.pz C.pz in between comparator output and uC input !!! voila even when reducing 8.3V to 50Ω the output rings to 3.6V
... ► 5pF (value of the parasitic capacitance) in between +,- inputs +,GND and OUTP to - input removes that crap ... in simulation (also removed parasitic inductor from OUTP to MOSFET inverter INP) . . . . but now there are pulse edge ringings up to 3.8V . . .
blah blah blah blah blaaah .....
there's some about such in
AN4071
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(here's what i managed to screw up
-- the mysterious L-s and C-s before R11 & R4 suppose to add wire maze effect ?? -- C1 C2 and C4 are intentional to minimize the maze . . . hopefully
)
it looks the inverting configuration can't do 2MHz
the component model a bit differs from the one on datasheet F;X
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2017-04-26 ::
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