Old Philips chip - PCC3505HP - ROM data latch, buffer, any info or help?

[jamesportman]

Hi,
Hope it's OK to ask for help as my first post, I just found this forum,

I am looking for more information or replacement for an IC I have here, attached a picture, I am referring to the top right IC.

The chip sits between a CPU which has 16 address/data lines, and a parallel ROM chip which has 16 address lines and 8 data lines out,
so it is doing some buffering between the two due to the limited number of bus lines on the CPU side.

It accepts a 16-bit/line address, holds that and passes it on to a ROM chip address lines, then accept 8 bits back from the ROM chip (while still holding the address (probably)), then passes the 8 bits back to the CPU. (When passing data back to the CPU it probably sends the 8 bit data back on lines 0-7 then leaves the rest as 0 I assume)
The CPU has a pin to mark "address valid", which I expect triggers the above to happen, I think it also has a pin for "external access" which would basically turn on the buffer and ROM chip (think chip enable pin).

The chip is marked with some info that is apparently not a part number, including:
PCC3530HP, 305272, DSD5449 A Y, TAIWAN.

The board in this case is from a Rover (English car) ECU, from around 1995.
The CPU in this case is the Intel AN87C196KD
The ROM is AT27C256 (AT27C256R?)



Summary:
Can anyone could even give me more information on what type of chip this is, or what it's called?

Edit: The closest thing I've seen so far is a tri-state buffer

Alternative: There are large pads for the CPU address/data lines so I could solder to those and use a completely different buffer and ROM chip as an option, but I need to figure out exactly what the buffer chip is, and to make something that acts in the same way/same timing.

Thanks for any help

 

[Pommie]

You might have more luck if you tell us what the CPU is.

Mike.
Edit and what the board is out of. Looks from around late 90s.

 

[jamesportman]

Thanks Mike, added board, CPU, ROM info to first post as you suggested

 

[jamesportman]

Well just an update of my progress anyway..
seems like the part numbers are custom/project specific, nobody including NXP have any idea what the chip is, or an alternative with the same pinout.

I'm just going to do it all myself on a daughter board with a new latch IC.
The ECU is expecting to have a ROM with 16 bit address but 8 bit data reads, so I will just use a new latch IC to capture the lower byte of the address bus, then send that latched lower byte and normal higher byte of address to the ROM, the CPU holds the upper address byte all the way through apparently, then use the CPU RD pin to enable the ROM output enable for it to send data back.

There is some combo of using the CPU READY pin and CPU chip config register to allow wait states in order to cover the ROM latency which is about 120ns,
hopefully able to just hold the READY pin low permanently then set number of waits in CCR.
The CPU does some weird method of attempting every possible read (16-bit, 8-bit) when it boots to get the CCR

 

[Pommie]

What are you trying to achieve? There are many micros that run at incredible speeds with huge amounts of flash and ram that are super cheap. You seem to be trying to reinvent the wheel.

Mike.

 

[jamesportman]

Yes I appreciate that, there are some projects like speeduino which I would use if going for new micro controller etc.

I am trying to just add a rewritable ROM chip (as opposed to the internal CPU OTP ROM) to an existing ECU which has had years of development gone into the existing code and board, and hopefully migrate the code over to new ROM in the process.
Some versions of this type of ECU did use a separate ROM chip so it's possible, just a case of getting the address latching right,
then dumping the original CPU data which is possible according to the CPU docs.

I have got as far as forcing the CPU to try to boot from external ROM and verified addresses being requested on the bus using a logic analyser, next step is to try a ROM dump.