noisy output of 74595 shift register

[MohsenTM]

hi friend i want chaining 22 or more 74595 and by these shift register only first 4 bit usage for driving a 4 channel relay module .
distance of module and shift register is 3 meter.74595 is a sub board on module every 3 meter.what circuit you recommended for this work.(excuse me for bad english)
my circuit is this.(i know is very simple).i made it for 12 meter (4 module,47595).output of 74595 is very noisy and not true.outputs every time changing by everything.
i know this circuit is not standard.
thank

 

[gophert]

Start by adding a 0.1 to 1.0 uF ceramic capacitor between pins 8 and 16 (power supply) within one inch of each chip - ideally even closer.

Also, add a 100 uF electrolytic in parallel with C1.

Also, change the low current 7805 regulator to a standard 7805 because 22 chips eventually consume a lot of power. Check the datasheet and multiply by 22 to understand your current demand.

If that doesn't help, there is more that can be done for power. The essential issue is that you do not have enough power and

 

[tvtech]

and..

Doing ETO on mobile is frustrating. To say the least.

 

[audioguru]

You wrote that you are using very old 74595 ICs that draw a high power supply current but your schematic shows newer 74HC595 Cmos ICs that draw a low power supply current.
Which ICs are you using?

 

[tvtech]

I've posts that miss words or spelling.

Hard to read.....rr...read

 

[rjenkinsgb]

With three metre long cables you will be getting transmission line effects - signal reflections and "ringing", which cause multiple transitions to be seen by the receiving logic.

That happens with any fast-changing signal from such as a logic IC, when sent over an unmatched connection with a significant length.
Ideally you should use impedance matched and terminated connections, but that gets complicated with multiple units.

You may get away with using a series R-C network on each signal line, to damp the ringing effect.
You really need an oscilloscope to look at the signals and adjust values until you can minimise the effects, but there are no guarantees it can work without significant design changes.

This is an example of the effect - the red is what you expect, the yellow is what you can actually get at the input with an unterminated or mismatched transmission line type connection (a piece of wire):
**broken link removed**

The ideal solution is to use purpose made line driver and receiver ICs for the data signals, which allow suitable matched resistive termination on the interconnecting cables, eg. the 26C31 & 26C32

They are rated for 10Mbit at up to 50ft (~15 metres) with appropriate cable.

https://www.ti.com/lit/ds/symlink/am26c31.pdf

https://www.ti.com/lit/ds/symlink/am26c32.pdf

 

[MohsenTM]

You wrote that you are using very old 74595 ICs that draw a high power supply current but your schematic shows newer 74HC595 Cmos ICs that draw a low power supply current.
Which ICs are you using?

i use 74HC595 Shift register of Texas semiconductor.

 

[MohsenTM]

i in each 3 meter, put a sub board and 1 module.on every sub board like that circuit one 78L05 for supply 74hc595 and 4 channel module. in the moment i want use one channel of module .
I have run this circuit on the bread board and it works. (For 4 74595).but by cable it is noisy.i put pull up 100k resistor in the first line for ST,SH,DS Noise was very low.

 

[MohsenTM]

With three metre long cables you will be getting transmission line effects - signal reflections and "ringing", which cause multiple transitions to be seen by the receiving logic.

That happens with any fast-changing signal from such as a logic IC, when sent over an unmatched connection with a significant length.
Ideally you should use impedance matched and terminated connections, but that gets complicated with multiple units.

You may get away with using a series R-C network on each signal line, to damp the ringing effect.
You really need an oscilloscope to look at the signals and adjust values until you can minimise the effects, but there are no guarantees it can work without significant design changes.

This is an example of the effect - the red is what you expect, the yellow is what you can actually get at the input with an unterminated or mismatched transmission line type connection (a piece of wire):
**broken link removed**

The ideal solution is to use purpose made line driver and receiver ICs for the data signals, which allow suitable matched resistive termination on the interconnecting cables, eg. the 26C31 & 26C32

They are rated for 10Mbit at up to 50ft (~15 metres) with appropriate cable.

https://www.ti.com/lit/ds/symlink/am26c31.pdf

https://www.ti.com/lit/ds/symlink/am26c32.pdf

thank
How can use Rc filters in the circuit. frequency MEGA8 internal RC 8M/HZ.

 

[rjenkinsgb]

How can use Rc filters in the circuit. frequency MEGA8 internal RC 8M/HZ.

Trial and error; you really need an oscilloscope to view the waveform and minimise overshoot..

I'd start with something like 1K and 100pF in series, between each signal pin and the ground on the same module.

 

[MohsenTM]

Start by adding a 0.1 to 1.0 uF ceramic capacitor between pins 8 and 16 (power supply) within one inch of each chip - ideally even closer.

Also, add a 100 uF electrolytic in parallel with C1.

Also, change the low current 7805 regulator to a standard 7805 because 22 chips eventually consume a lot of power. Check the datasheet and multiply by 22 to understand your current demand.

If that doesn't help, there is more that can be done for power. The essential issue is that you do not have enough power and

control unite (micro and ...) has separate Power supply and sub board & module separate supply (78L05).

 

[MohsenTM]

Is it possible to relay 74HC595 with a single 78L05? (In each module and sub-board)

 

[MohsenTM]

Trial and error; you really need an oscilloscope to view the waveform and minimise overshoot..

I'd start with something like 1K and 100pF in series, between each signal pin and the ground on the same module.

I can go to university and use the lab there.but It is difficult to carry the circuit and the wires.
excuse me. can you show me by a image how can series cap & res between each signal?
if not give answer this way I'm forced to go lab.

 

[rjenkinsgb]

can you show me by a image series cap & res between each signal?

See figure 4 on page 4 of this article for the concept; a series resistor and capacitor from each signal input at the "load" end of the cable connection, to the circuit ground at that point.

https://fenix.tecnico.ulisboa.pt/downloadFile/3779579943588/

Another problem is that your link cables are random impedance, apparently with signals adjacent to each other.
For a high speed data connection, ideally you would use alternate cores with grounds in between (or pairs of cores, with balanced drivers) and ribbon cable, for consistent and predictable characteristics.

 

[MohsenTM]

https://fenix.tecnico.ulisboa.pt/downloadFile/3779579943588/

this is very good reference . for my work.
tnx

 

[MohsenTM]

24/5000



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