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Need help in Xilinx ISE schematic

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rose

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Hi,
I would like to perform my own memory in Xilinx ISE using shematic to store values of matrix.To perform my memory I'll associate blocks Look Up Table (LUTs) with only one input.

My problem is that when I realize a test in modelsim for one LUT I always have 0 at the output of LUT whatever the bit in the input .How can I get the same bit in the input and output?

Thank you.
 
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