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Need help designing a monostable circuit using comparators.

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ItsMike

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Hello everyone,

I'm trying to design a monostable circuit (one shot) using lm 339 comparators.
The voltage source is 28-30v so I can't use any lm555's or anything.

I have 2 spare comparators in the quad package.
 
Hello everyone,

I'm trying to design a monostable circuit (one shot) using lm 339 comparators.
The voltage source is 28-30v so I can't use any lm555's or anything.

I have 2 spare comparators in the quad package.

hi,
Is the mono trigger an edge or a level.?? hi or low going trigger level, what period for the mono timing.?
 
Hi,

Just a quick note...

You can use a 555 if you really wanted to, by dropping some voltage to run the 555 and then using a transistor on the output for the higher voltage drive.
 
I really wouldn't mind if it's edge or level triggered.
I would like it to trigger on high voltage (or rising edge) and I still need to measure the period and calibrate the one shot for it with a trimmer or change the cap or whatever.

(Basically the one shot circuit is part of motor over current protection, it should make the current sense circuit ignore the motor starting period and thus ignore the motor start peak current.)

I tried simulating the monostable circuit from the datasheet but ltspice produced weird results or it failed to simulate it.
 
Hi again Mike,

If you really want to reproduce the 555 internals you should be able to do that, but you have to realize that they use a flip flop too inside there. If you use two comparators and one flip flop you can get it exactly like the 555. Perhaps a waste of parts though for a simple one shot.

The simplest one shot is made from an inverter or buffer and a capacitor in series with a resistor, driven from say another inverter or buffer. The cap is in series with the input so that when the input changes state current flows through the cap and creates a voltage across the resistor and that drives the second inverter or buffer. Usually a Schmitt trigger input inverter or buffer would be used for the second stages, but it works with regular gates too. If you use comparators it should be easy as you just have to have them react to the current flow through the cap for that brief pulse time. A little hysteresis and you should get a good output pulse.
 
Last edited:
I tried simulating the monostable circuit from the datasheet but ltspice produced weird results or it failed to simulate it.

Mike,
Post your LTS asc file and I will give it a run thru.
 
I might have deleted the one i built from the datasheet, but here is one i built from some circuit i found on the web.

comparator model i used:
Code:
* WARNING : please consider following remarks before usage
*
* 1) All models are a tradeoff between accuracy and complexity (ie. simulation 
*    time).
* 2) Macromodels are not a substitute to breadboarding, they rather confirm the
*    validity of a design approach and help to select surrounding component values.
*
* 3) A macromodel emulates the NOMINAL performance of a TYPICAL device within 
*    SPECIFIED OPERATING CONDITIONS (ie. temperature, supply voltage, etc.).
*    Thus the macromodel is often not as exhaustive as the datasheet, its goal
*    is to illustrate the main parameters of the product.
*
* 4) Data issued from macromodels used outside of its specified conditions
*    (Vcc, Temperature, etc) or even worse: outside of the device operating 
*    conditions (Vcc, Vicm, etc) are not reliable in any way.
*-----------------------------------------------------------------------------------------
* LM139/LM239/LM339 spice macromodel
* CONNECTIONS :
* 1 NON-INVERTING INPUT
* 2 INVERTING INPUT
* 3 POSITIVE POWER SUPPLY
* 4 NEGATIVE POWER SUPPLY
* 5 OUTPUT
*
**********************************************************
.SUBCKT LMx39 2 1 44 55 30
EVCCP 4 0 44 0 1.0
EVCCN 5 0 55 0 1.0
VREADIO 3 30 DC 0
G_ICCSAT 44 55 VALUE={2.1E-4+3E-6*V(44,55)}
G_IOUT_SINKED 55 0 VALUE={IF (V(1)<V(2), 0, I(VreadIo))}
.MODEL MDTH D IS=1E-11 KF=1.050321E-32 CJO=10F
* INPUT STAGE
CIP 2 5 1.000000E-12
CIN 1 5 1.000000E-12
EIP 102 0 2 0 1
VIO 10 102 438.3U
EIN 16 0 1 0 1
RIP 10 11 6.500000E+01
RIN 15 16 6.500000E+01
RIS 11 15 1.939046E+02
DIP 11 12 MDTH 400E-12
DIN 15 14 MDTH 400E-12
VOFP 12 13 DC 0.000000E+00
VOFN 13 14 DC 0
IPOL 13 0 100E-06
CPS 11 15 5.5E-09
DINN 17 13 MDTH 400E-12
VIN 17 5 0.000000e+00
DINR 15 18 MDTH 400E-12
VIP 4 18 1.500000E+00
FCP 4 5 VOFP 0.175 
FCN 5 4 VOFN 0.175 
FIBP 2 0 VOFN 4.000000E-04
FIBN 0 1 VOFP 4.000000E-04
* AMPLIFYING STAGE
RG1 5 19 2.85E+05
RG2 4 19 2.85E+05
DOP 19 25 MDTH 400E-12
VOP 4 25 1.097
DON 24 19 MDTH 400E-12
VON 24 5 1.097
FIP 0 19 VOFP -104 
FIN 0 19 VOFN -104
EOUT 26 5 19 5 1 
.MODEL NMOD NPN(IS=0.1E-09 BF=4000)
RBOUT 27 26 800K
QOUT 103 27 28 28 NMOD
REOUT 28 5 20
RSOUT 3 0 1E+12
VNUL 3 103 0
DSTOP 32 103 MDTH 400E-12
HSTOP 32 33 VNUL 135
VSTOP 33 5 0.5
.ENDS
 

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  • Draft1.asc
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hi Mike,
The circuit using those components will not work with a 5V trigger pulse.
Look at this option, increase Ct for longer mono ON periods, Rth sets the trigger threshold.

I would use a 20Kpot for Rth.

What is the output pulse connected to.?
 

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The output should be connected to another comparator's output thus "ANDing" them (open collector).
If that's not possible I could use a transistor for that.

Also, what would it take to invert the trigger ? Currently it needs the trigger to go from high to low, what would be the easiest way of flipping it ?
The source of the trigger is an op amp.
And I still have one free comparator.

Thanks.
 
hi,
The simple way is an inverting transistor.
 

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Thanks alot guys.

Also, one last question... this is more ltspice related.
Why does the output signal biased at +3v ? Could it be that the comparator model you use is bugged ?
I had that happen with couple of comparator models, untill i came a cross the model above in which the signal is not biased.
 
Thanks alot guys.

Also, one last question... this is more ltspice related.
Why does the output signal biased at +3v ? Could it be that the comparator model you use is bugged ?
I had that happen with couple of comparator models, untill i came a cross the model above in which the signal is not biased.
hi,
Its the 'dview' multi plot that appears to show an 3v offset.!
Look at this image for the actual pulse
Dont you use a the dview for multiple traces.
 

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Actually I never heard of dview, im kind of new to ltspice.

hi,
I dont follow what you are saying.?

You have edited your post while I was replying
 
Last edited:
I got confused for what is the trigger soruce. I forgot it wont be a 5v analog signal but a 28v pulse.
That's why I edited the last post.

Anyways, thanks a lot.
 
Last edited:
I got confused for what is the trigger soruce. I forgot it wont be a 5v analog signal but a 28v pulse.
That's why I edited the last post.

Anyways, thanks a lot.

Use a higher value resistor to the base and/or a resistive divider
 
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