Here is a more detailed explanation of what I thought SHOULD happen. Correct me if I am wrong
1. Normal Idle state (diring the zero crossing interval). Data register outputs are tri-stated, cap is charged high, and fed to NOR gate. Second NOR gate input is also high (from zero cross detector, so output to triac (or opto-coupler-driver) is turned off.
2. After zero crossing, zero cross output goes low gating out data register bits which, depending on their state, drain the cap to a point where the NOR gate input is active low which when coupled with the zero cros detector output low, allows the NOR gate to change output state to drive the triac for the remainder of the current AC half cycle.
3. As the next zero cross nears, the zero cross detector output goes high, which shuts off the NOR gate output, allowing the triac to shut down at zero crossing.
Originally, I intended for the R2R DAC output to be fed to a schmitt trigger (74xx14) and then to a NOR gate, but I posted the schematic in a functional form for simplicity of understanding, instead of the actual components to be used.
Does this make more sense, and can this variable timing trigger delay be
done with off the shelf components and still be kept relatively simple?
Thanks
Dialtone