9.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 9-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 9-4.
The maximum recommended impedance for analog
sources is 10 kΩ. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 9-1 may be used. This equation
assumes that 1/2 LSb error is used (1024 steps for the
ADC). The 1/2 LSb error is the maximum error allowed
for the ADC to meet its specified resolution.
19.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 19-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
To calculate the minimum acquisition time,
Equation 19-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 19-3 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system
assumptions:
CHOLD = 120 pF
Rs = 2.5 kΩ
Conversion Error ≤ 1/2 LSb
VDD = 5V → Rss = 7 kΩ
Temperature = 50°C (system max.)
VHOLD = 0V @ time = 0
The inputs do work, but seem to 'sink' the voltage on the input when approaching 5 volts. Also unconnected inputs seem to vary in sympathy with the voltage applied to connected input.
What sort of value cap would you recommend?With analogue inputs that are not changing quickly, it is always a good idea to put a capacitor between each input and ground. That is because the ADC takes a pulse of current as it reads, and because if you are getting any noise, the input clamping diodes may be conducting and lowering the voltage.
What sort of value cap would you recommend?
You need to change thisCode:TRISA = 0x1F; to TRISA =0xFF;
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current
...
.....You need to read the data sheet starting at page 249
On the drawing you posted it shows Pins 2 to 10 being use as Analog You need to set PORTA as input in the code you posted you only have 5 of them set
0x1F = b'00011111' 0xFF = b'11111111'
Looking at page 250 of the datasheet, it looks to me like bits 7, 6 should be 00 as they are unimplemented, bit 5 is the voltage ref, since I am not using external voltage ref, it should be 0, bit 4 ditto, bits 3- 0 according to the look up table on that page:You have ADCON1 0x00 it should be 0x0F And I wouldn't even use a hex value I would us B'00001111' easy see whats there
Here I am not 100%, but my 'guru' says If I set ADCON2 as above, it will sample the pins at twice the speed, so instead of slowing down the sample rate, it's being sped up.ADCON2 needs to be B'10100111' This would give you time to get a reading your settings was way to fast you have TAD as 0
...
You need to read the data sheet starting at page 249
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