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MOSFET paralleling advice?

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Mosaic

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Hi all:

I am planning to parallel 4 (on a common large Heatsink) of these:
https://www.electro-tech-online.com/custompdfs/2013/01/irlb3036pbf.pdf

to carry (1) A load of about 100A (12.6V) for 15 sec.
and (2) A load of about 5A to 20A for 30 min.

The 100A load is resistive (0.125 ohms)and requires the MOSFETS to be fully on, no PWM.

For item (2) I am using a 7Khz PWM drive (0-4.5V) thru a 3 stage pi filter into the Gate drives as a control signal.

I have an Allegro Hall Sensor giving current feedback (to an MCu) for control:
https://www.newark.com/allegro-micr...or-pff-5/dp/04R7132?in_merch=Popular Products


I just wanted some advice on whether I need to worry about MOSFET load balancing. Given the currents involved I don't want to use limiting resistors.


Here's what I have figured so far:

I note the Rds ranges from 1.9 to 2.4 mOhms for about a 25% max differential @ steady state.
Does this mean that up to 25% more power can be dissipated in one of the FETS? If so once this peak is within the FET ratings then all should be ok?

So for 100A/4 = 25A. Then worst case is 25 *1.25 = 31.25A. Power dissip = I^2* R = 31.25*31.25 *.0024 = 2.34W, or 0.46W extra.

At 20A, then voltage drop across the FETs = 10.1V => a parallel .0505 ohms which is about 2.02 ohms Rds each (based on the PWM gate drive V). Now 0.0005 ohms worst case Rds difference shouldn't matter much here as it's just .0025% of the throttled Rds.

Is that sound design?
 
Last edited:
It sounds like for item 2 you are trying to run the FETs in the linear region. If that's true it will be a problem, mostly due to the variation in the gate threshold voltages of the FETs.
 
If you don't want to use limiting resistors the only alternatives I can see would be (a) four separate current-control loops or (2) use a single higher-rated FET.
 
Yep, As alec says 4 sensors and 4 op amps to compare to your micro signal. Those sensors are nice - expensive, but nice. :D
 
Ok, I split the original limiting load into 4 equal resistive loads on the source to ground lines. Then added a PWM referenced opamp [ -ve feedback control based on the resistive voltage drop at the source junction] to drive each gate. How does that sound?
 
Any particular reason for having the loads in the source to ground lines rather than the (more conventional) Vdd to drain lines?
 
Ok, I split the original limiting load into 4 equal resistive loads on the source to ground lines. Then added a PWM referenced opamp [ -ve feedback control based on the resistive voltage drop at the source junction] to drive each gate. How does that sound?

That will work if the 4 different loads are close to equal.
 
You need 4 separate loads in the sources if you are going to do it this way and the op amp voltage must be able to drive higher than the turn on voltage of the FET plus the voltage drop across the load at the desired current. It looks like your op amp will only run from 5 volts. The threshold for your FETs can be between 1 to 2.5 volts at very low current so if you drop much voltage across the load resistors it won't work. It is the same variation in gate threshold voltage that keeps you from using one load in the source of the 4 FETs.
Maybe a schematic would be a good idea to make sure we are talking about the same things.
 
Schematic

Have a look at this.
 

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